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important notice dear customer, as from june 1 st , 2007 nxp semiconductors has acquired the lh7xxx arm microcontrollers from sharp microelectronics. the following changes are applicable to the attached data sheet. in data sheets where the previous sharp or sharp corp oration references remain, please use the new links as shown below. for www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use salesaddresses@nxp.com (email) the copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - copyright ? ( year ) by sharp corporation. is replaced with: - ? nxp b.v. ( year ). all rights reserved. if you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com ). thank you for your cooperation and understanding, in addition to that the annex a (attached hereto) is added to the document. nxp semiconductors
product data sheet 1 lh7a404 product data sheet 32-bit system-on-chip features ? 32-bit arm9tdmi? risc core ? 16 kb cache: 8 kb instruction and 8 kb data cache ? mmu (windows ce? enabled) ? up to 266 mhz; see table 1 for speed options ? 80 kb on-chip static ram ? vectored interrupt controller ? external bus interface ? up to 133 mhz; see table 1 for bus speed options ? asynchronous and synchronous interface ram, flash, pc card and compactflash ? clock and power management ? 32.768 khz and 14. 7456 mhz oscillators ? programmable pll ? programmable lcd controller ? up to 1,024 768 resolution ? supports stn, color stn, ad-tft, hr-tft, tft ? up to 64 k-colors and 15 gray shades ? 9 channel, 10-bit a/d converter ? touch screen controller ? brownout detector ? dma (12 channels) ? external dma channels ?ac97 ?mmc ?usb ? usb 2.0 full speed host (two downst ream ports) ? usb 2.0 full speed device ? synchronous serial port (ssp) ? motorola spi?, texas instruments ssi, national semiconductor microwire? ? on-board boot rom ? variety of boot modes: external rom, nand flash, serial eeprom, or xmodem ? ps/2 keyboard/mouse interface (kmi) ? three programmable timers ? three uarts, one with cl assic irda (115 kbit/s) ? smart card interface (iso7816) ? four pulse width modulators (pwms) ? multimediacard interface with secure digital (mmc 2.11/sd 1.0) ? ac97 codec interface ? smart battery monitor interface ? real time clock (rtc) ? up to 64 general purpose i/o channels ? watchdog timer ? jtag debug interface and boundary scan ? operating voltage ? 1.8 v (200 mhz), 2.1 v (266 mhz) core ? 3.3 v input/output (except xtalin is 1.8 v) ? 5 v tolerant digital inputs (excludes oscillator pins) ? oscillator pins t19, t20, y18, y19: 1.8 v 10 % ? operating temperature: ? 40c to +85c ? 324-ball lfbga package description the advent of 3g technology opens up a wide range of multimedia applications in mobile information appli- ances. the lh7a404 is designed from the ground up with a 32-bit arm922 core to provide high processing performance, low power consumption, and a high level of integration. features include 80 kb on-chip sram, fully static design, power management unit, low voltage (1.8 v core, 3.3 v i/o) and on-chip pll. note: devices containing lead-free sol der formulations have differ- ent reflow temperatures than leaded-solder formulations. when using both solder formulat ions on the same pc board, designers should consid er the effect of different reflow tem- peratures on the overall pcb assembly process. (refer to www.nxp.com for an application note on recommended soldering practices). notes: 1. where ?xx? is a two digit re vision number, e.g. b2; refer to www.nxp.com for a list of all the active revisions 2. lead-free part. table 1. lh7a404 versions part number 1 core clock bus clock low po wer current by mode version lh7a404-n0f-092-xx 2 266 mhz 133 mhz run = 228 ma (typ.); ha lt = 60 ma (typ.); standby = 200 ? a (typ.) sot1021-1 lh7a404-n0f-000-xx 2 200 mhz 100 mhz run = 147 ma (typ.); ha lt = 41 ma (typ.); standby = 70 ? a (typ.) sot1021-1
lh7a404 32-bit system-on-chip 2 product data sheet nxp semiconductors figure 1. lh7a404 block diagram lh7a404-1 oscillator, pll1 and pll2, power management, and reset control vectored interrupt controller real time clock 14.7456 mhz 32.768 khz synchronous memory controller pcmcia/cf controller color lcd controller 80kb sram lcd ahb bus asynchronous memory controller external bus interface arm 922t advanced peripheral bus bridge dma controller boot controller boot rom advanced high-performance bus (ahb) advanced perpheral bus (apb) advanced lcd interface (ali) usb host interface general purpose i/o (64) synchronous serial port timer (3) battery monitor interface usb device interface watchdog timer irda interface uart (3) multimediacard/ secure digital interface smart card interface (iso7816) pwm (2) ps2 keyboard/mouse interface a/d touch screen controller codec interface dc to dc interface (2) ac97 lh7a404
32-bit system-on-chip lh7a404 product data sheet 3 nxp semiconductors table 2. lh7a404 functional pin list lfbga signal description reset state standby state output drive i/o notes e10 vdd i/o ring power e11 h10 h11 k5 k8 k13 k16 l5 l8 l13 l16 n10 n11 t10 t11 u18 j9 vss i/o ring ground j10 j11 j12 k9 k10 k11 k12 l9 l10 l11 l12 m9 m10 m11 m12 t18 e7 vddc core power e9 e14 g5 g16 p5 p16 t7 t12 t14
lh7a404 32-bit system-on-chip 4 product data sheet nxp semiconductors e6 vssc core ground e15 f5 f16 j16 m5 r5 r16 t6 t15 y17 vdda analog power for pll1 and pll2 w17 v16 vssa analog ground for pll1 and pll2 u15 w16 vddad analog power for a/d, touch screen controller v13 vssad analog ground for a/d, touch screen controller d2 npor power on reset input input i 3 e1 nureset user reset input input i 3 f3 wakeup wake up input input i 3 f4 npwrfl power fail signal input input i 3 c1 nextpwr external power input input i 3 c5 nresetout reset output to external dev ices. this pin carries the same state as the internal soc reset signal. low 12 ma o y18 xtalin 14.7456 mhz crystal oscillator pins. for an external clock source, xtalin can be used while xtalout is left unconnected. xtalin voltage is 1.8 v nominal. y19 xtalout t19 xtal32in 32.768 khz real time clock, crystal oscillator pins. to drive the device from an external clock source, xtal32in can be used while xtal32out is left unconnected. t20 xtal32out l2 pgmclk programmable clock (14.7456 mhz max.) low low 8 ma o t16 clken external oscillator enable output low low 8 ma i/o y13 width0 boot width pins. used with the medchg and int- boot bits for internal boot rom. on power up, the values on these pins are latched to determine the width and type of boot devic e. boot width can be 8-, 16-, or 32-bit. the pins must be pulled high with a 33 k ? resistor. input input i 3 w13 width1 e4 medchg media change bit; used at power on with intboot and widthx pins to determine boot device. input no change i 3 y20 intboot when low, boot device is selected according to the medchg bit. when high, the lower 64 kb address- es are mapped to the internal boot rom. input no change i table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes
32-bit system-on-chip lh7a404 product data sheet 5 nxp semiconductors n19 d0 data bus low low 12 ma i/o p20 d1 n18 d2 n20 d3 m16 d4 m18 d5 l18 d6 l17 d7 l19 d8 j19 d9 k17 d10 j18 d11 h19 d12 g20 d13 g19 d14 h17 d15 f19 d16 e20 d17 e19 d18 d20 d19 e18 d20 c20 d21 d18 d22 b20 d23 c18 d24 a20 d25 b18 d26 c16 d27 b17 d28 a18 d29 a17 d30 b15 d31 p17 a0 asynchronous address bus high low 12 ma o n16 a1 table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes
lh7a404 32-bit system-on-chip 6 product data sheet nxp semiconductors n17 a2/sa0 asynchronous address bus and synchronous address bus low low 12 ma o m19 a3/sa1 m20 a4/sa2 l20 a5/sa3 m17 a6/sa4 k18 a7/sa5 k20 a8/sa6 k19 a9/sa7 j20 a10/sa8 h20 a11/sa9 j17 a12/sa10 h18 a13/sa11 f20 a14/sa12 g18 a15/sa13 h16 a16/sb0 ? asynchronous address bus ? synchronous device bank address 0 low low 12 ma o f18 a17/sb1 ? asynchronous address bus ? synchronous device bank address 1 low low 12 ma o g17 a18 asynchronous address bus low low 12 ma o f17 a19 d19 a20 asynchronous address bus low low 12 ma o 4 e17 a21 c19 a22 asynchronous address bus low low 12 ma o d17 a23 b19 a24 a16 a25 d15 a26 b14 a27 v18 ncs0 asynchronous memory chip select 0 high high 12 ma o r19 ncs1 asynchronous memory chip select 1 high high 12 ma o r18 ncs2 asynchronous memory chip select 2 high high 12 ma o p19 ncs3 asynchronous memory chip select 3 high high 12 ma o r20 ncs6 asynchronous memory chip select 6 high no change 12 ma o r17 ncs7 asynchronous memory chip select 7 high no change 12 ma o c12 noe asynchronous memory output enable high high 12 ma o 4 d12 nwe asynchronous memory write enable high high 12 ma o 4 p18 nwait asynchronous memory wait; pull high if unused input no change i 5 c17 nscs0 synchronous memory ch ip select 0 high high 12 ma i/o a19 nscs1 synchronous memory chip select 1 high high 12 ma i/o d16 nscs2 synchronous memory ch ip select 2 high high 12 ma i/o e16 nscs3 synchronous memory chip select 3 high high 12 ma i/o b16 nswe synchronous memory write enable high high 12 ma o a14 scke0 clock enable 0 for synchr onous memory high no change 12 ma o b13 scke1_2 clock enable 1 or 2 for sy nchronous memory high no change 12 ma o table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes
32-bit system-on-chip lh7a404 product data sheet 7 nxp semiconductors c14 scke3 clock enable 3 for synchronous memory depends on medchg low 12 ma i/o d14 sclk synchronous memory clock low no change 20 ma i/o 2 a13 nble0 byte lane enable 0 high high 12 ma i/o u9 nble1 byte lane enable 1 high high 12 ma o y7 nble2 byte lane enable 2 high high 12 ma o c13 nble3 byte lane enable 3 high high 8 ma o c15 ncas synchronous memory column address strobe high high 12 ma i/o a15 nras synchronous memory row address strobe high high 12 ma i/o d13 dqm0 data mask for synchronous memories high no change 12 ma o e13 dqm1 b12 dqm2 a12 dqm3 m2 pa0/ lcdvd16 ? gpio port a0 ? lcd data pin 16 pa0: input no change 8 ma i/o l4 pa1/ lcdvd17 ? gpio port a1 ? lcd data pin 17 pa1: input no change 8 ma i/o m3 pa2 gpio port a[6:2] pax: input no change 8 ma i/o m4 pa3 m1 pa4 n3 pa5 n2 pa6 n1 pa7 ? gpio port a7 ? boot width selection (see table 6) pa7: input no change 8 ma i/o 4 n4 pb0/uartrx1 ? gpio port b0 ? uart1 receive data input pb0: input no change 8 ma i/o p3 pb1/uarttx3 ? gpio port b1 ? uart3 transmit data out pb1: input no change 8 ma i/o p2 pb2/uartrx3 ? gpio port b2 ? uart3 receive data in pb2: input no change 8 ma i/o p1 pb3/uartcts3 ? gpio port b3 ? uart3 clear to send pb3: input no change 8 ma i/o r3 pb4/uartdcd3 ? gpio port b4 ? uart3 data carrier detect pb4: input no change 8 ma i/o n5 pb5/uartdsr3 ? gpio port b5 ? uart3 data set ready pb5: input no change 8 ma i/o r2 pb6/swid/smbd ? gpio port b6 ? single wire data ? smart battery data pb6: input no change 8 ma i/o r1 pb7/smbclk ? gpio port b7 ? smart battery clock pb7: input no change 8 ma i/o p4 pc0/uarttx1 ?gpio port c0 ? uart1 transmit data output pc0: low no change 12 ma i/o t1 pc1 gpio port c[5:1] pcx: low no change 12 ma i/o t2 pc2 t3 pc3 r4 pc4 u1 pc5 u2 pc6 gpio port c6 pc6: low no change 12 ma i/o 4 table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes
lh7a404 32-bit system-on-chip 8 product data sheet nxp semiconductors v1 pc7 gpio port c7 pc7: low no change 12 ma i/o y11 pd0/lcdvd8 ? gpio port d[7:0] ? lcd video data interface pdx: low low if 8-bit lcd enabled; else no change 12 ma i/o u10 pd1/lcdvd9 w12 pd2/lcdvd10 v11 pd3/lcdvd11 w11 pd4/lcdvd12 u11 pd5/lcdvd13 v12 pd6/lcdvd14 y12 pd7/lcdvd15 y9 pe0/lcdvd4 ? gpio port e[3:0] ? lcd video data interface pex: output low if 8-bit lcd enabled; else no change 12 ma i/o w10 pe1/lcdvd5 v10 pe2/lcdvd6 t9 pe3/lcdvd7 d4 pe4/scclkin ? gpio port e4 ? smart card push-pull mode clock input pe4: output no change 12 ma i/o c3 pe5/scclken ? gpio port e5 ? smart card push-pull mode external clock buffer enable pe5: output no change 12 ma i/o b2 pe6/scin ? gpio port e6 ? smart card push-pull mode data input pe6: output no change 12 ma i/o a1 pe7/scdaten ? gpio port e7 ? smart card push-pull mode data out external buffer enable pe7: output no change 12 ma i/o a9 pf0/int0 ?gpio port f0 ? interrupt 0 pf0: input no change 8 ma i/o 3 d9 pf1/int1 ?gpio port f1 ? interrupt 1 pf1: input no change 8 ma i/o 3 a8 pf2/int2 ?gpio port f2 ? interrupt 2 pf2: input no change 8 ma i/o 3 c8 pf3/int3 ?gpio port f3 ? interrupt 3 pf3: input no change 8 ma i/o 3 b8 pf4/int4 ?gpio port f4 ? interrupt 4 pf4: input no change 8 ma i/o 3 d8 pf5/int5/ scdetect ?gpio port f5 ? interrupt 5 ? smart card interface card detect signal pf5: input no change 8 ma i/o 3 a7 pf6/int6/ pcrdy1 ?gpio port f6 ? interrupt 6 ? ready for card 1 for pc card (pcmcia or compactflash) in single or dual card mode pf6: input no change 8 ma i/o 3 e8 pf7/int7/pcrdy2 ?gpio port f7 ? interrupt 7 ? ready for card 2 for pc card (pcmcia or compactflash) in single or dual card mode pf7: input no change 8 ma i/o 3 y2 pg0/npcoe ?gpio port g0 ? output enable for pc card (pcmcia or compactflash) in single or dual card mode low no change 8 ma i/o w4 pg1/npcwe ?gpio port g1 ? write enable for pc card (pcmcia or compactflash) in single or dual card mode low no change 8 ma i/o table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes
32-bit system-on-chip lh7a404 product data sheet 9 nxp semiconductors y3 pg2/npcior ?gpio port g2 ? i/o read strobe for pc card (pcmcia or compactflash) in single or dual card mode low no change 8 ma i/o u5 pg3/npciow ?gpio port g3 ? i/o write strobe for pc card (pcmcia or compactflash) in single or dual card mode low no change 8 ma i/o t5 pg4/npcreg ?gpio port g4 ? register memory access fo r pc card (pcmcia or compactflash) in single or dual card mode low no change 8 ma i/o w5 pg5/npcce1 ?gpio port g5 ? card enable 1 for pc card (pcmcia or compactflash) in single or dual card mode. this signal and npcce2 are used by the pc card for decoding low and high byte accesses. low no change 8 ma i/o y4 pg6/npcce2 ?gpio port g6 ? card enable 2 for pc card (pcmcia or compactflash) in single or dual card mode. this signal and npcce1 are used by the pc card for decoding low and high byte accesses. low no change 8 ma i/o w6 pg7/pcdir ?gpio port g7 ? direction for pc card (pcmcia or compactflash) in single or dual card mode low no change 8 ma i/o v6 ph0/pcreset1 ?gpio port h0 ? reset card 1 for pc card (pcmcia or compactflash) in single or dual card mode phx: input no change 8 ma i/o y5 ph1/cfa8/ pcreset2 ?gpio port h1 ? address bit 8 for pc card (compactflash) in single card mode ? reset card 2 for pc card (pcmcia or compactflash) in dual card mode phx: input no change 8 ma i/o w7 ph2/npcslote1 ?gpio port h2 ? enable card 1 for pc card (pcmcia or compactflash) in single or dual card mode. this signal is used for gating ot her control signals to the appropriate pc card. phx: input no change 8 ma i/o u6 ph3/cfa9/ pcmciaa25/ npcslote2 ?gpio port h3 ? address bit 9 for pc card (compactflash) in single card mode ? address bit 25 for pc card (pcmcia) in single card mode ? enable card 2 for pc card (pcmcia or compactflash) in dual card mode. used for gating other control signals to the appropriate pc card. phx: input no change 8 ma i/o w8 ph4/npcwait1 ?gpio port h4 ? wait signal for card 1 for pc card (pcmcia or compactflash) in single or dual card mode phx: input no change 8 ma i/o y6 ph5/cfa10/ pcmciaa24/ npcwait2 ?gpio port h5 ? address bit 10 for pc card (compactflash) in sin- gle card mode ? address bit 24 for pc card (pcmcia) in single card mode ? wait signal for card 2 for pc card (pcmcia or compactflash) in dual card mode phx: input no change 8 ma i/o v7 ph6/nac97reset ?gpio port h6 ? ac97 reset phx: input no change 8 ma i/o table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes
lh7a404 32-bit system-on-chip 10 product data sheet nxp semiconductors u7 ph7/ npcstatre ?gpio port h7 ? status read enable for pc card (pcmcia or compactflash) in single or dual card mode phx: input no change 8 ma i/o t4 lcdfp/lcdsps ? lcd frame pulse ? ali reset row driver counter low low if not in ali mode 12 ma o v2 lcdlp/ lcdhrlp ? lcd linepulse ? ali latch pulse low low if not in ali mode 12 ma o u3 lcdcls ali clock for row drivers low no change 12 ma o v3 lcdspl ali start pulse left for reverse scanning low no change 12 ma o u4 lcdubl ali up, down signal for reverse scanning low no change 12 ma o w1 lcdspr ali start pulse right for normal scanning low no change 12 ma o v4 lcdlbr ali output for reverse scanning high no change 12 ma o w2 lcdmod ali mod signal used by the row driver low no change 12 ma o v5 lcdps ali power save high no change 12 ma o y1 lcdvdden ali power sequence control low no change 12 ma o w3 lcdrev ali reverse high no change 12 ma o u8 lcdclkin external clock input for lcd controller input no change i v8 lcdvd0 lcd video data interface low low 12 ma o t8 lcdvd1 w9 lcdvd2 y8 lcdvd3 v9 lcdenab/ lcdm ? lcd tft data enable ? lcd stn ac bias low low 12 ma o y10 lcddclk lcd pixel clock low low 12 ma o u17 usbdcp usb device full speed pull-up resistor control input input 12 ma i u20 usbdp usb device data positive (differential pair) input input 12 ma i/o u19 usbdn usb device data negative (differential pair) input input 12 ma i/o w19 usbhdp0 usb data host positive 0 (differential pair) input high 12 ma i/o w20 usbhdn0 usb data host negative 0 (differential pair) input low 12 ma i/o v19 usbhdp1 usb data host positive 1 (differential pair) input input 12 ma i/o v20 usbhdn1 usb data host negative 1 (differential pair) input input 12 ma i/o t17 usbhpwr usb host power; this pin is connected to the remote usb host power switch?s enable pin. in response to a fault condition, signalled on the nusbhovrcurr pin, the lh7a404 can assert this pin, which causes the power switch shut down. low no change 12 ma o v17 nusbhovrcurr usb host overcurrent; the overcurrent input is used to indicate to the host a fault has occurred, resulting in current limiting. the lh7a404 can be programmed to cause the remote power switch to shut off by assert- ing usbhpwr in response to an nusbhovrcurr assertion. input input 12 ma i d11 npwme0 dc-dc converter 0 pwm 0 enable input input 8 ma i/o a10 npwme1 dc-dc converter 1 pwm 1 enable input input 8 ma i/o c11 pwm0 dc-dc converter 0 output (pulse width modulated) low input 8 ma i/o c10 pwm1 dc-dc converter 1 output (pulse width modulated) low input 8 ma i/o b9 pwm2 pwm output 2 low no change 8 ma o d10 pwm3 pwm output 3 low no change o c9 pwmsync pwm synchronizing input for pwm2 input no change 8 ma i table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes
32-bit system-on-chip lh7a404 product data sheet 11 nxp semiconductors c7 acbitclk ? audio codec (ac97) clock ? audio codec (aci) clock input no change 8 ma i/o b7 acout ? audio codec (ac97) output ? audio codec (aci) output low low 8 ma o a6 acsync ? audio codec (ac97) synchronization ? audio codec (aci) synchronization low low 8 ma o b6 acin ? audio codec (ac97) input ? audio codec (aci) input input no change 8 ma i/o a5 mmcclk multimediacard clock (20 mhz max.) low low 8 ma i/o d7 mmccmd multimediacard command input input 8 ma i/o c6 mmcdata0 multimediacard data 0 input input 8 ma i/o b5 mmcdata1 multimediacard data 1 input input 8 ma i/o a4 mmcdata2 multimediacard data 2 input input 8 ma i/o b4 mmcdata3 multimediacard data 3 input input 8 ma i/o f2 uartcts2 uart2 clear to send signal input input 8 ma i/o f1 uartdcd2 uart2 data carrier detect signal input input 8 ma i/o g2 uartdsr2 uart2 data set ready signal input input 8 ma i/o g3 uartirtx1 irda transmit low no change 8 ma i/o g1 uartirrx1 irda receive input input 8 ma i/o h2 uarttx2 uart2 transmit data output high no change 8 ma i/o g4 uartrx2 uart2 receive data input input input 8 ma i/o k3 sspclk synchronous serial port clock low low 8 ma o l1 ssprx synchronous serial port receive input input 8 ma i/o l3 ssptx synchronous serial port transmit input input 8 ma i/o k4 sspfrm synchronous serial port frame sync high high 8 ma o j2 col0 keyboard interface high high 8 ma i/o h4 col1 h5 col2 j1 col3 j3 col4 j4 col5 j5 col6 k2 col7 e2 batok battery ok input input i 3 d1 nbatchg battery change input input i 3 u12 batcntl battery control for a/d controller battery monitor low no change 12 ma o h1 kmidat keyboard/mouse data input no change 12 ma i/o h3 kmiclk keyboard/mouse clock input no change 12 ma i/o k1 tbuz timer buzzer output (254 khz max.) low low 8 ma i/o y16 an0/ul/x+ ? adc channel 0 ? touch screen controller upper left ? touch screen controller x-plus input input i y15 an1/ur/x- ? adc channel 1 ? touch screen controller upper right ? touch screen controller x-minus input input i w14 an2/ll/y+ ? adc channel 2 ? touch screen controller lower left ? touch screen controller y-plus input input i table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes
lh7a404 32-bit system-on-chip 12 product data sheet nxp semiconductors notes: 1. signals beginning with ?n? are active low. 2. the sclk pin can source up to 12 ma and sink up to 20 ma. see ?dc characteristics?. 3. schmitt trigger input; see ?dc spec ifications?, page 31 for triggers points and hysteresis. 4. these pins have alternate na nd flash functions during boot-up when using the internal boot rom. consult the boot rom chapter of the user?s guide for more information. 5. the nwait pin must be pulled high with a 33 k ? resistor to avoid the possibility of the smc i nadvertently going into wait. 6. the internal pullup and pulldown resistance on all digital i/o pins is 50k ? . u13 an3/lr/y- ? adc channel 3 ? touch screen controller lower right ? touch screen controller y-minus input input i v14 an4/wiper ? adc channel 4 ? wiper input from 5-wire touch screen input input i u14 vss or vssa connect pin to either vss or vssa input input i v15 an6 adc channel 6 input input i w15 an7 adc channel 7 input input i t13 an8 adc channel 8 input input i y14 an9 adc channel 9 input input i e12 scio smart card interface i/o low low 12 ma i/o a11 scclk smart card interface clock low low 12 ma i/o b11 nscreset smart card interface reset low low 12 ma o b10 scvccen smart card interface vcc enable low no change 12 ma o d6 ctclkin counter timer clock input input no change i a3 dreq0 dma request 0 input no change i d5 dack0 dma acknowledge 0 input no change 12 ma i/o c4 deot0 dma end of transfer 0 input no change 12 ma i/o b3 dreq1 dma request 1 input no change i a2 dack1 dma acknowledge 1 input no change 12 ma i/o e5 deot1 dma end of transfer 1 input no change 12 ma i/o u16 ntest0 test pin 0. internal weak pull up to vdd. status latched at npor going high. pull low for jtag mode. pull high (or leave open) for normal mode. see table 3. input with pull-up input with pull-up i w18 ntest1 test pin 1. internal weak pull up to vdd. status latched at npor going high. pull high (or leave open) for both jtag and normal mode. see table 3. input with pull-up input with pull-up i d3 tdi jtag data in. internal weak pull up to vdd. input no change i c2 tck jtag clock. internal weak pull up to vdd. input no change i 3 b1 tdo jtag data out high z no change 4 ma o e3 tms jtag test mode select. internal weak pull up to vdd. input no change i table 2. lh7a404 functional pin list (cont?d) lfbga signal description reset state standby state output drive i/o notes table 3. ntest pin function mode ntest0 ntest1 nureset jtag 0 1 1 normal 1 1 x
32-bit system-on-chip lh7a404 product data sheet 13 nxp semiconductors notes: 1. the intensity bit is identical ly generated for all three colors. 2. mustn = monochrome upper panel mlstn = monochrome lower panel custn = color upper panel clstn = color lower panel table 4. lcd controller pins lfbga pin reset state lcd signal stn tft ad-tft/ hr-tft mono 4-bit mono 8-bit color single panel dual panel single panel dual panel single panel dual panel l4 pa1 lcdvd17 low m2 pa0 lcdvd16 low y12 pd7 lcdvd15 mlstn7 clstn7 intensity intensity v12 pd6 lcdvd14 mlstn6 clstn6 blue4 blue4 u11 pd5 lcdvd13 mlstn5 clstn5 blue3 blue3 w11 pd4 lcdvd12 mlstn4 clstn4 blue2 blue2 v11 pd3 lcdvd11 mlstn3 clstn3 blue1 blue1 w12 pd2 lcdvd10 mlstn2 clstn2 blue0 blue0 u10 pd1 lcdvd9 mlstn1 clstn1 green4 green4 y11 pd0 lcdvd8 mlstn0 clstn0 green3 green3 t9 pe3 lcdvd7 mlstn3 mustn7 mustn7 custn7 custn7 green2 green2 v10 pe2 lcdvd6 mlstn2 mustn6 mustn6 custn6 custn6 green1 green1 w10 pe1 lcdvd5 mlstn1 mustn5 mustn5 custn5 custn5 green0 green0 y9 pe0 lcdvd4 mlstn0 mustn4 mustn4 custn4 custn4 red4 red4 y8 lcdvd3 lcdvd3 mustn3 mustn3 mustn3 mustn3 custn3 custn3 red3 red3 w9 lcdvd2 lcdvd2 mustn2 mustn2 mustn2 mustn2 custn2 custn2 red2 red2 t8 lcdvd1 lcdvd1 mustn1 mustn1 mustn1 mustn1 custn1 custn1 red1 red1 v8 lcdvd0 lcdvd0 mustn0 mustn0 mustn0 mustn0 custn0 custn0 red0 red0 u3 lcdcls lcdcls lcdcls y10 lcddclk lcddclk lcddclk lcddclk lcddclk lcddclk lcddclk lcddclk lcddclk lcddclk t4 lcdfp lcdfp/ lcdsps lcdfp lcdfp lcdfp lcdfp lcdfp lcdfp lcdfp lcdsps v2 lcdlp lcdlp/ lcdhrlp lcdlp lcdlp lcdlp lcdlp lcdlp lcdlp lcdlp lcdhrlp w2 lcdmod lcdmod lcdmod v5 lcdps lcdps lcdps w3 lcdrev lcdrev lcdrev v3 lcdspl lcdspl lcdspl v4 lcdlbr lcdlbr lcdlbr w1 lcdspr lcdspr lcdspr u4 lcdubl lcdubl lcdubl y1 lcdvdden lcdvdden lcdvdden u8 lcdclkin lcdclkin lcdclkin lcdclkin lcdclkin lcdclkin lcdclkin lcdclkin lcdclkin lcdclkin v9 lcdenab lcdenab/ lcdm lcdm lcdm lcdm lcdm lcdm lcdm lcdenab
lh7a404 32-bit system-on-chip 14 product data sheet nxp semiconductors table 5. lfbga numerical pin list lfbga signal slew rate output drive a1 pe7/scdaten 95 mv/ns 12 ma a2 dack1 95 mv/ns 12 ma a3 dreq0 a4 mmcdata2 110 mv/ns 8 ma a5 mmcclk 110 mv/ns 8 ma a6 acsync 110 mv/ns 8 ma a7 pf6/int6/pcrdy1 110 mv/ns 8 ma a8 pf2/int2 110 mv/ns 8 ma a9 pf0/int0 110 mv/ns 8 ma a10 npwme1 95 mv/ns 12 ma a11 scclk 95 mv/ns 12 ma a12 dqm3 110 mv/ns 8 ma a13 nble0 95 mv/ns 12 ma a14 scke0 95 mv/ns 12 ma a15 nras 95 mv/ns 12 ma a16 a25 95 mv/ns 12 ma a17 d30 95 mv/ns 12 ma a18 d29 95 mv/ns 12 ma a19 nscs1 95 mv/ns 12 ma a20 d25 95 mv/ns 12 ma b1 tdo 100 mv/ns 4 ma b2 pe6/scin 95 mv/ns 12 ma b3 dreq1 b4 mmcdata3 110 mv/ns 8 ma b5 mmcdata1 110 mv/ns 8 ma b6 acin 110 mv/ns 8 ma b7 acout 110 mv/ns 8 ma b8 pf4/int4 110 mv/ns 8 ma b9 pwm2 110 mv/ns 8 ma b10 scvccen 95 mv/ns 12 ma b11 nscreset 95 mv/ns 12 ma b12 dqm2 95 mv/ns 12 ma b13 scke1_2 95 mv/ns 12 ma b14 a27 95 mv/ns 12 ma b15 d31 95 mv/ns 12 ma b16 nswe 95 mv/ns 12 ma b17 d28 95 mv/ns 12 ma b18 d26 95 mv/ns 12 ma b19 a24 95 mv/ns 12 ma b20 d23 95 mv/ns 12 ma c1 nextpwr c2 tck c3 pe5/scclken 95 mv/ns 12 ma c4 deot0 95 mv/ns 12 ma c5 nresetout c6 mmcdata 110 mv/ns 8 ma c7 acbitclk 110 mv/ns 8 ma c8 pf3/int3 110 mv/ns 8 ma c9 pwmsync c10 pwm1 110 mv/ns 8 ma c11 pwm0 110 mv/ns 8 ma c12 noe 95 mv/ns 12 ma c13 nble3 110 mv/ns 8 ma c14 scke3 95 mv/ns 12 ma c15 ncas 95 mv/ns 12 ma c16 d27 95 mv/ns 12 ma c17 nscs0 95 mv/ns 12 ma c18 d24 95 mv/ns 12 ma c19 a22 95 mv/ns 12 ma c20 d21 95 mv/ns 12 ma d1 nbatchg d2 npor d3 tdi d4 pe4/scclkin 95 mv/ns 12 ma d5 dack0 95 mv/ns 12 ma d6 ctclkin d7 mmccmd 110 mv/ns 8 ma d8 pf5/int5/scdetect 110 mv/ns 8 ma d9 pf1/int1 110 mv/ns 8 ma d10 pwm3 110 mv/ns 8 ma d11 npwme0 110 mv/ns 8 ma d12 nwe 95 mv/ns 12 ma d13 dqm0 95 mv/ns 12 ma d14 sclk 190 mv/ns 20 ma d15 a26 95 mv/ns 12 ma d16 nscs2 95 mv/ns 12 ma d17 a23 95 mv/ns 12 ma d18 d22 95 mv/ns 12 ma d19 a20 95 mv/ns 12 ma d20 d19 95 mv/ns 12 ma e1 nureset e2 batok e3 tms e4 medchg e5 deot1 95 mv/ns 12 ma e6 vssc e7 vddc e8 pf7/int7/pcrdy2 110 mv/ns 8 ma e9 vddc e10 vdd table 5. lfbga numerical pin list (cont?d) lfbga signal slew rate output drive
32-bit system-on-chip lh7a404 product data sheet 15 nxp semiconductors e11 vdd e12 scio 95 mv/ns 12 ma e13 dqm1 95 mv/ns 12 ma e14 vddc e15 vssc e16 nscs3 95 mv/ns 12 ma e17 a21 95 mv/ns 12 ma e18 d20 95 mv/ns 12 ma e19 d18 95 mv/ns 12 ma e20 d17 95 mv/ns 12 ma f1 uartdcd2 110 mv/ns 8 ma f2 uartcts2 110 mv/ns 8 ma f3 wakeup f4 npwrfl f5 vssc f16 vssc f17 a19 95 mv/ns 12 ma f18 a17/sbank1 95 mv/ns 12 ma f19 d16 95 mv/ns 12 ma f20 a14/sa12 95 mv/ns 12 ma g1 uartirrx1 110 mv/ns 8 ma g2 uartdsr2 110 mv/ns 8 ma g3 uartirtx1 110 mv/ns 8 ma g4 uartrx2 110 mv/ns 8 ma g5 vddc g16 vddc g17 a18 95 mv/ns 12 ma g18 a15/sa13 95 mv/ns 12 ma g19 d14 95 mv/ns 12 ma g20 d13 95 mv/ns 12 ma h1 kmidat 95 mv/ns 12 ma h2 uarttx2 110 mv/ns 8 ma h3 kmiclk 95 mv/ns 12 ma h4 col1 100 mv/ns 8 ma h5 col2 100 mv/ns 8 ma h10 vdd h11 vdd h16 a16/sbank0 95 mv/ns 12 ma h17 d15 95 mv/ns 12 ma h18 a13/sa11 95 mv/ns 12 ma h19 d12 95 mv/ns 12 ma h20 a11/sa9 95 mv/ns 12 ma j1 col3 100 mv/ns 8 ma j2 col0 100 mv/ns 8 ma j3 col4 100 mv/ns 8 ma table 5. lfbga numerical pin list (cont?d) lfbga signal slew rate output drive j4 col5 100 mv/ns 8 ma j5 col6 100 mv/ns 8 ma j9 vss j10 vss j11 vss j12 vss j16 vssc j17 a12/sa10 95 mv/ns 12 ma j18 d11 95 mv/ns 12 ma j19 d9 95 mv/ns 12 ma j20 a10/sa8 95 mv/ns 12 ma k1 tbuz 110 mv/ns 8 ma k2 col7 100 mv/ns 8 ma k3 sspclk 110 mv/ns 8 ma k4 sspfrm 110 mv/ns 8 ma k5 vdd k8 vdd k9 vss k10 vss k11 vss k12 vss k13 vdd k16 vdd k17 d10 95 mv/ns 12 ma k18 a7/sa5 95 mv/ns 12 ma k19 a9/sa7 95 mv/ns 12 ma k20 a8/sa6 95 mv/ns 12 ma l1 ssprx 110 mv/ns 8 ma l2 pgmclk 110 mv/ns 8 ma l3 ssptx 110 mv/ns 8 ma l4 pa1/lcdvd17 110 mv/ns 8 ma l5 vdd l8 vdd l9 vss l10 vss l11 vss l12 vss l13 vdd l16 vdd l17 d7 95 mv/ns 12 ma l18 d6 95 mv/ns 12 ma l19 d8 95 mv/ns 12 ma l20 a5/sa3 95 mv/ns 12 ma m1 pa4 110 mv/ns 8 ma m2 pa0/lcdvd16 110 mv/ns 8 ma table 5. lfbga numerical pin list (cont?d) lfbga signal slew rate output drive
lh7a404 32-bit system-on-chip 16 product data sheet nxp semiconductors m3 pa2 110 mv/ns 8 ma m4 pa3 110 mv/ns 8 ma m5 vssc m9 vss m10 vss m11 vss m12 vss m16 d4 95 mv/ns 12 ma m17 a6/sa4 95 mv/ns 12 ma m18 d5 95 mv/ns 12 ma m19 a3/sa1 95 mv/ns 12 ma m20 a4/sa2 95 mv/ns 12 ma n1 pa7 110 mv/ns 8 ma n2 pa6 110 mv/ns 8 ma n3 pa5 110 mv/ns 8 ma n4 pb0/uartrx1 110 mv/ns 8 ma n5 pb5/uartdsr3 110 mv/ns 8 ma n10 vdd n11 vdd n16 a1 95 mv/ns 12 ma n17 a2/sa0 95 mv/ns 12 ma n18 d2 95 mv/ns 12 ma n19 d0 95 mv/ns 12 ma n20 d3 95 mv/ns 12 ma p1 pb3/uartcts3 110 mv/ns 8 ma p2 pb2/uartrx3 110 mv/ns 8 ma p3 pb1/uarttx3 110 mv/ns 8 ma p4 pc0/uarttx1 95 mv/ns 12 ma p5 vddc p16 vddc p17 a0 95 mv/ns 12 ma p18 nwait p19 ncs3 95 mv/ns 12 ma p20 d1 95 mv/ns 12 ma r1 pb7/smbclk 110 mv/ns 8 ma r2 pb6/swid/smbd 110 mv/ns 8 ma r3 pb4/uartdcd3 110 mv/ns 8 ma r4 pc4 95 mv/ns 12 ma r5 vssc r16 vssc r17 ncs7 95 mv/ns 12 ma r18 ncs2 95 mv/ns 12 ma r19 ncs1 95 mv/ns 12 ma r20 ncs6 95 mv/ns 12 ma t1 pc1 95 mv/ns 12 ma table 5. lfbga numerical pin list (cont?d) lfbga signal slew rate output drive t2 pc2 95 mv/ns 12 ma t3 pc3 95 mv/ns 12 ma t4 lcdfp/lcdsps 95 mv/ns 12 ma t5 pg4/npcreg 110 mv/ns 8 ma t6 vssc t7 vddc t8 lcdvd1 95 mv/ns 12 ma t9 pe3/lcdvd7 95 mv/ns 12 ma t10 vdd t11 vdd t12 vddc t13 an8 t14 vddc t15 vssc t16 clken 110 mv/ns 8 ma t17 usbhpwr 95 mv/ns 12 ma t18 vss t19 xtal32in t20 xtal32out u1 pc5 95 mv/ns 12 ma u2 pc6 95 mv/ns 12 ma u3 lcdcls 95 mv/ns 12 ma u4 lcdubl 95 mv/ns 12 ma u5 pg3/npciow 110 mv/ns 8 ma u6 ph3/cfa9/pcmciaa25/ npcslote2 110 mv/ns 8 ma u7 ph7/npcstatre 110 mv/ns 8 ma u8 lcdclkin u9 nble1 95 mv/ns 12 ma u10 pd1/lcdvd9 95 mv/ns 12 ma u11 pd5/lcdvd13 95 mv/ns 12 ma u12 batctl 95 mv/ns 12 ma u13 an3/lr/y- u14 vss or vssa u15 vssa u16 ntest0 u17 usbdcp u18 vdd u19 usbdn u20 usbdp v1 pc7 95 mv/ns 12 ma v2 lcdlp/lcdhrlp 95 mv/ns 12 ma v3 lcdspl 95 mv/ns 12 ma v4 lcdlbr 95 mv/ns 12 ma v5 lcdps 95 mv/ns 12 ma table 5. lfbga numerical pin list (cont?d) lfbga signal slew rate output drive
32-bit system-on-chip lh7a404 product data sheet 17 nxp semiconductors v6 ph0/pcreset1 110 mv/ns 8 ma v7 ph6/nac97reset 110 mv/ns 8 ma v8 lcdvd0 95 mv/ns 12 ma v9 lcdenab/lcdm 95 mv/ns 12 ma v10 pe2/lcdvd6 95 mv/ns 12 ma v11 pd3/lcdvd11 95 mv/ns 12 ma v12 pd6/lcdvd14 95 mv/ns 12 ma v13 vssad v14 an4/wiper v15 an6 v16 vssa v17 nusbhovrcurr v18 ncs0 95 mv/ns 12 ma v19 usbhdp1 v20 usbhdn1 w1 lcdspr 95 mv/ns 12 ma w2 lcdmod 95 mv/ns 12 ma w3 lcdrev 95 mv/ns 12 ma w4 pg1/npcwe 110 mv/ns 8 ma w5 pg5/npcce1 110 mv/ns 8 ma w6 pg7/pcdir 110 mv/ns 8 ma w7 ph2/npcslote1 110 mv/ns 8 ma w8 ph4/npcwait1 110 mv/ns 8 ma w9 lcdvd2 95 mv/ns 12 ma w10 pe1/lcdvd5 95 mv/ns 12 ma w11 pd4/lcdvd12 95 mv/ns 12 ma w12 pd2/lcdvd10 95 mv/ns 12 ma table 5. lfbga numerical pin list (cont?d) lfbga signal slew rate output drive w13 width1 w14 an2/ll/y+ w15 an7 w16 vddad w17 vdda w18 ntest1 w19 usbhdp0 w20 usbhdn0 y1 lcdvdden 95 mv/ns 12 ma y2 pg0/npcoe 110 mv/ns 8 ma y3 pg2/npcior 110 mv/ns 8 ma y4 pg6/npcce2 110 mv/ns 8 ma y5 ph1/cfa8/pcreset2 110 mv/ns 8 ma y6 ph5/cfa10/pcmciaa24/ npcwait2 110 mv/ns 8 ma y7 nble2 95 mv/ns 12 ma y8 lcdvd3 95 mv/ns 12 ma y9 pe0/lcdvd4 95 mv/ns 12 ma y10 lcddclk 95 mv/ns 12 ma y11 pd0/lcdvd8 95 mv/ns 12 ma y12 pd7/lcdvd15 95 mv/ns 12 ma y13 width0 y14 an9 y15 an1/ur/x- y16 an0/ul/x+ y17 vdda y18 xtalin y19 xtalout y20 intboot table 5. lfbga numerical pin list (cont?d) lfbga signal slew rate output drive
lh7a404 32-bit system-on-chip 18 product data sheet nxp semiconductors system descriptions arm922t processor the lh7a404 microcontroller features the arm922t cached core with an adv anced high-performance bus (ahb) interface. the processor is a member of the arm9t family of processors. for more information, see the arm document, ?arm922t technical reference manual?, available on arm? s website at www.arm.com. clock and state controller the clocking scheme in the lh7a404 is based around two primary oscillator inputs. these are the 14.7456 mhz input crystal and the 32.768 khz real time clock oscillator; see figure 3. the 14.7456 mhz oscil- lator supplies the main sys tem clock domains for the lh7a404. the 32.768 khz oscillator controls the power-down operations and real time clock peripheral. the clock and state controller provides the clock gating and frequency division necessary, and then supplies the clocks to the processor and rest of the system. the amount of clock gating that actually takes place depends on the power saving mode selected. the 32.768 khz clock provides the source for the real time clock tree and power-down logic. this clock is used for the power state control and is the only clock in the lh7a404 that runs continuously. the 32.768 khz clock is divided down to 1 hz for the real time clock counter using a ripple divider to save power. the 14.7456 mhz source is used to generate the main system clocks for the lh7a404. it is the source for pll1 and pll2, the primary clock for the peripher- als, and the source clock to the programmable clock (pgm) divider. pll1 provides the main clock tree for the chip. it gen- erates the following clocks: fclk, hclk, and pclk. fclk is the clock that drives the arm922t core. hclk is the main bus (ahb) clock, as such it clocks all memory interfaces, bus arbitrators and the ahb peripherals. hclk is generated by dividing fclk by 1, 2, 3, or 4. hclk can be gated by the system to enable low power operation. pclk is the peripheral bus (apb) clock. it is gener- ated by dividing hclk by either 2, 4, or 8. pll2 generates a fixed 48 mhz clock signal for the usb peripheral. figure 2. application diagram codec battery dc to dc voltage generation circuitry multimedia card mmc/sd sci pcmcia compact flash usb host device host sdram sram rom flash dma ac97 stn/tft/ ad-tft ir gpio ssp uart lh7a404 pc card lh7a404-2 1 2 3 4 5 6 7 8 9 * 0 # bmi smart card touch screen contr.
32-bit system-on-chip lh7a404 product data sheet 19 nxp semiconductors power modes the lh7a404 has three operational states: run, halt, and standby. during run all clocks are hardware enabled and the processor is clocked. in the halt mode the device is functioning, but the processor clock is halted while it waits for an event such as a key press. standby equates to the computer being switched ?off?, i.e. no display (lcd disabl ed) and the main oscillator is shut down. reset modes three external signals can generate resets to the lh7a404: npor (power on reset), npwrfl (power failure) and nureset (user reset). if any of these are active, a system reset is internally generated. an npor reset performs a full system reset. the npwrfl and nureset resets perform a full system reset except for the sdram refresh control, sdram global configura- tion, sdram device configuration, and the rtc peripheral registers. the sdram controller issues a self-refresh command to external sdram before the system enters an npwrfl and nureset reset. this allows the system to mainta in its real time clock and sdram contents. upon release of reset, the chip enters standby mode. once in the run mode the pwrsr register can be interrogated to determine the nature of the reset and the trigger source, after which software can then take appropriate actions. data paths the data paths in the lh7a404 are: ? the amba ahb bus ? the amba apb bus ? the external bus interface ? the lcd ahb bus ? the dma busses. amba ahb bus the advanced microprocessor bus architecture ahb (amba ahb) is a high speed 32-bit-wide data bus. the amba ahb is for high- performance, high-clock-fre- quency system modules. lh7a404 peripherals and memory with high band- width requirements are connected to the arm922t processor and other bus masters using a multi-master ahb bus. these peripherals include the external mem- ory interfaces, on-chip sram, lcd controller (bus master), dma controller (bus master), and usb host (bus master). remaining peripherals reside on the lower bandwidth advanced peripheral bus (apb), which is accessed from the ahb via the apb bridge. the apb bridge is the only master on th e apb, and its operation is transparent to the user as it converts ahb accesses into slower apb accesses automatically. figure 3. clock and state controller block diagram ?in 14.7456 mhz lh7a404-6 500 khz min. hclkdiv gclk must be between 80 and 400 mhz pclkdiv fclk hclk hclk_cpu pclk 32.768 khz rtc osc gate gate divide by prediv+2 divide by 2 ps vco pll1 main divider 1: divide by maindiv1+2 main divider 2: divide by maindiv2+2 32.768 khz rtc
lh7a404 32-bit system-on-chip 20 product data sheet nxp semiconductors amba apb bus the amba apb provides a lower-bandwidth bus for peripherals accessed less freq uently. this reduces the loading on the ahb, allowing it to run faster to maxi- mize system performance, while the apb can operate at a lower clock rate to conserve power. the apb bridge is the only master on the apb. all ahb masters can access apb peripherals via the abp bridge. the apb clock frequency can be selected by software to divide the clock speed of the ahb bus by 2, 4, or 8. external bus interface (ebi) the external bus interface (ebi) provides a 32-bit- wide, high speed gateway to external memory devices. the supported memory devices include: ? asynchronous ram/rom/flash ? synchronous dram/flash ? pcmcia interfaces ? compactflash interfaces. the ebi can be controlled by either the asynchro- nous memory controller or synchronous memory con- troller. there is an arbiter on the ebi input, with priority given to the synchronous memory controller interface. lcd bus the lcd controller has its own local memory bus that connects it to the system?s embedded memory and external sdram. the function of this local data bus is to allow the lcd controller to perform its video refresh function without congesting the main ahb bus. this leads to better system performance and lower power consumption. there is an arbiter on both the embed- ded memory and the synchronous memory controller. in both cases the lcd bus is given priority. dma buses the lh7a404 has a dma system that connects the higher speed/higher data volume apb peripherals (mmc, usb device and ac97) to the ahb bus. this enables the efficient transfer of data between these peripherals and external memory without the interven- tion of the arm922t core. usb host controller dma bus the usb host controller has its own dma control- ler. it acts as another bus master on the ahb bus. it does not interact with the non-usb dma controller except in bus arbitration. memory map the lh7a404 system has a 32-bit-wide address bus, allowing addressing up to 4gb of memory. this mem- ory space is subdivided into a number of memory banks, shown in figure 4. four of these banks (each 256mb) are allocated to the synchronous memory controller. eight banks (each 256mb) are allocated to the asynchronous memory controller. two of these eight banks are designed for pcmcia systems. part of the remaining memory space is allocated to the embed- ded sram, and to the control registers of the ahb and apb. the rest of the memory space is not used. the lh7a404 can boot from both internal and exter- nal devices. the selection is determined by the value of five pins at power-on reset as shown in table 6. if boot- ing is from an external device (with intboot = 0), refer to table 7. when booting from external synchro- nous memory, bank 4 (nscs3) is mapped into memory location zero. when booting from external asynchro- nous memory, memory bank 0 (nscs0) is mapped into memory location zero. figure 4 shows the memory map of the lh7a404 system for the two boot modes. once the lh7a404 has booted, the boot code can configure the arm922t mmu to remap the low mem- ory space to a location in ra m. this allows the user to set the interrupt vector table.
32-bit system-on-chip lh7a404 product data sheet 21 nxp semiconductors table 6. internal boot modes boot device gpio pa7 latched medchg latched width1 latched width0 latched intboot external device see table 7 0 8-bit interface, 3-byte address nand flash 0 0 0 0 1 8-bit interface, 4-byte address nand flash 0 0 0 1 1 8-bit interface, 5-byte address nand flash 0 0 1 0 1 16-bit interface, 3-byte address nand flash 1 0 0 0 1 16-bit interface, 4-byte address nand flash 1 0 0 1 1 16-bit interface, 5-byte address nand flash 1 0 1 0 1 xmodem using uart2 0 1 0 0 1 i 2 c eeprom 0 1 0 1 1 undefined 00 1 1 1 01 1 1 1 10 1 1 1 11 x x 1 table 7. external boot modes boot mode medchg width1 width0 intboot 8-bit rom 0 0 0 0 16-bit rom 0 0 1 0 32-bit rom 0 1 0 0 invalid: do not allow this condition. 0 1 1 0 16-bit synchflash (initializes device mode register) 1 0 0 0 16-bit srom (initializes device mode register) 1 0 1 0 32-bit synchflash (initializes device mode register) 1 1 0 0 32-bit srom (initializes device mode register) 1 1 1 0 boot from internal boot rom; see table 6 x x x 1
lh7a404 32-bit system-on-chip 22 product data sheet nxp semiconductors vectored interrupt controller (vic) the lh7a404 has two vics working together to manage interrupt requests from on-chip and off-chip sources. each vic performs these primary functions: ? determine if an interrupt source is disabled or can generate an fiq or irq to the arm core ? prioritize up to 16 separate interrupt sources for simultaneous and nested processing ? obtain the address of the interrupt handler (vector) for up to 16 interrupt sources ? provide a default vector and a set of status registers for up to 16 non-vectored sources. software deter- mines the priority of these interrupts. two vics are daisy-chained together to support up to 64 different interrupts, 32 of which are vectored. the vic supports both fiq and irq interrupts. fiq inter- rupts have a higher priority than irq interrupts. if two interrupts with the same priority become active at the same time, the priority must be resolved in software. when an interrupt becomes active, the vic generates an fiq or irq if the corresponding mask bit is set. interrupts are not latched in the vic, but may latch on a particular peripheral when applicable. after a power-on reset, all mask register bits are cleared, masking all interrupts. they must be set by software after power-on reset to enable interrupts. a vectored interrupt has improved latency as it pro- vides direct information about where its service routine is located and eliminates software arbitration needed with a simple interrupt controller. the vics continue to operate in halt and standby modes, so external interrupts may bring the chip out of these low power modes. external bus interface the arm922t, lcd controller, and dma engine have access to an extern al memory system. the lcd controller has access to an internal frame buffer in embedded sram and an extension buffer in synchro- nous memory for large displays. the processor and dma engine share the main system bus, providing access to all external memo ry devices and the embed- ded sram frame buffer. an arbitration unit ensures that control over the external bus interface (ebi) is only granted when an existing access has been completed. see figure 4. figure 4. external bus interface block diagram arm922t lcd controller embedded sram 80kb lcd ahb bus system ahb bus lcd mmu/dma dma controller usb host asynchronous memory controller (smc) synchronous memory controller (sdmc) external bus interface (ebi) arbiter sdram sram sdram rom data address/ control lh7a404-8 internal to the lh7a404 external to the lh7a404
32-bit system-on-chip lh7a404 product data sheet 23 nxp semiconductors embedded sram the lh7a404 incorporates 80 kb of embedded sram. this embedded memory is used for storing code, data, or lcd frame data and is contiguous with external sdram. the 80 kb is large enough to store a qvga frame (320 240) at 8 bits per pixel, equivalent to 70 kb of information. locating the frame buffer on chip reduces the overall power consumed by lh7a404 applications. normally, the system performs external accesses to acquire this data. the lcd controller automatically uses an over- flow frame buffer in sdram if a larger screen size is required. this overflow buffer can be located on any 4 kb page boundary in sdram, allowing software to set the mmu (in the lcd controller) page tables so the two memory areas appear contiguous, allowing byte, half-word, and word accesses. static memory controller (smc) the asynchronous static memory controller (smc) provides an interface between the amba ahb system bus and external (off-chip) memory devices. the smc simultaneously supports up to eight inde- pendently configurable memo ry banks. each memory bank can support: ?sram ?rom ? flash eprom ? burst rom memory. each memory bank may use devices with either 8-, 16-, or 32-bit external memory data paths. the memory controller is configur ed to support little-endian operation only. the memory banks can be configured to support: ? non-burst read and write accesses only to high- speed cmos static ram ? non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. the smc has six main functions: ? memory bank select ? access sequencing ? wait state generation ? byte lane write control ? external bus interface ? compactflash or pcmcia interfacing. sdram (synchronous) memory controller the sdram (synchronous) memory controller pro- vides a high speed memory interface to a wide variety of synchronous memory devices, including synchronous dram, synchronous flash and synchronous roms. the key features of the controller are: ? lcd dma port for high bandwidth ? up to four synchronous memory banks can be inde- pendently set up ? includes special configuration bits for synchronous rom operation ? includes ability to progr am synchronous flash devices using write and erase commands ? on booting from synchronous rom, (and optionally with synchronous flash), a configuration sequence is performed before releasing the processor from reset ? data is transferred between the controller and the synchronous dram in four-word bursts. longer transfers within the same page are concatenated, forming a seamless burst ? programmable for 16- or 32-bit data bus size ? two reset domains enable synchronous dram con- tents to be preserved over a ?soft? reset ? power saving synchronous memory scke and external clock modes provided. secure digital/mu ltimediacard (mmc) the sd memory card is a flash-based memory card that meets the security, capacity, performance, and environment requirements inherent in electronic devices. the sd memory card host supports multimediacard (mmc) operation as well, and is com- patible with mmc cards. the sd/mmc controller can be used as an mmc card controller or as an sd card controller, and sup- ports the full sd/mmc bus protocol as defined in the mmc system specification 2.11 provided by the mmc association and the ?sd memory card spec v1.0? from the sd association.
lh7a404 32-bit system-on-chip 24 product data sheet nxp semiconductors sd/mmc interface description the sd/mmc controller uses the three-wire signal bus (clock, command, and data) to input and output data to and from the mmc, and to configure and acquire status information from the card. the sd con- troller differs in that it has four data lines instead of one. the sd/mmc bus lines can be divided into three groups: ? power supply: vss1, vss2, and vdd ? data transfer group: mmccmd, mmcdata0, mmcdata1, mmcdata2, mmcdata3 (for mmc, do not use mmcdata1, mmcdata2, mmcdata3) ? clock: mmcclk mmc controller the mmc controller implemen ts mmc-specific func- tions, serves as the bus master for the mmc bus and implements the standard interface to the mmc (card initialization, crc generation and validation, com- mand/response transactions, etc.). smart card interface (sci) the sci (iso7816) connects to an external smart card reader. the sci can autonomously control data transfer to and from the smart card. transmit and receive data fifos are provided to reduce the required interaction between the cpu core and the peripheral. sci features ? supports asynchronous t0 and t1 transmission protocols ? supports clock rate conversion factor f = 372, with bit rate adjustment factors of d = 1, 2, or 4 ? eight-character-deep buffered tx and rx paths ? direct interrupts for tx a nd rx fifo level monitoring ? interrupt status register ? hardware-initiated card deactivation sequence on detection of card removal ? software-initiated card deactivation sequence on transaction complete ? limited support for synchronous smart cards via reg- istered input/output. programmable parameters ? smart card clock frequency ? communication baud rate ? protocol convention ? card activation/deactivation time ? maximum time for first character of answer to reset (atr) reception checking ? maximum atr character stream duration checking ? maximum time of receipt of first character of data stream checking ? maximum time allowed between characters checking ? character guard time ? block guard time ? ? transmit/receive character retry. direct memory access controller (dma) the dma controller can be used to interface streams from 20 internal peripherals to the system memory using 10 fully-independent programmable channels which consist of fi ve m2p (transmit) channels and five p2m (receive) channels. the following peripherals may be allocated to the 10 channels: ? usb device ? usb host ? sd/mmc ? ac97 ?uart1 ?uart2 ?uart3 each of the above peripherals contain one tx and one rx channel, except the ac97, which contains three tx and rx channels. these pe ripherals also have their own bi-directional dma bus, capable of simultaneously transferring data in both directions. all memory trans- fers take place via the main system ahb bus. the dma controller can also be used to interface streams from memory-to-memory (m2m) or memory- to-external peripheral (m2p) using two dedicated m2m channels. external handshake signals are avail- able to support memory-to-/from-external peripheral (m2p/p2m) transfers. a software trigger is available for m2m transfers only.
32-bit system-on-chip lh7a404 product data sheet 25 nxp semiconductors the dma controller features: ? two dedicated channels for m2m and external m2p/p2m ? ten fully independent, programmable dma control- ler internal m2p/p2m channels (5 tx and 5 rx) ? channels assignable to one of a number of different peripherals ? independent source and destination address regis- ters. source and destination can be programmed to auto-increment or not auto-increment for m2m channels ? two buffer descriptors per m2p and m2m channel to avoid potential data under/over-flow due to software introduced latency. a buffer refers to the area in sys- tem memory that is characterized by a buffer descriptor, i.e., a start address and the length of the buffer in bytes ? no amba wrapping bursts for dma channels; only incrementing bursts are supported ? buffer size independent of the peripheral?s packet size for the internal m2p channels. transfers can automatically switch between buffers ? maskable interrupt generation ? internal arbitration between dma channels, plus support for an ahb bus arbiter ? dma data transfer sizes, byte, word and quad-word data transfers are supported using a 16-byte data. maximum data transfer size per m2m channel is programmable ? per-channel clock gating reducing power in chan- nels that have not been enabled by software. see the ?clock and state co ntroller? section. a set of control and status registers are available to the system processor for se tting up dma operations and monitoring their status. system interrupts are gen- erated when any/all of the dma channels wish to inform the processor to update the buffer descriptor. the dma controller can service 10 out of 20 possible peripherals using the ten dma channels, each with its own peripheral dma bus capable of simultaneously transferring data in both directions. the sd/mmc, uart[3:1], usb device, and usb host peripherals can each use two dma channels, one for transmit and one for receive. the ac97 peripheral can use six dma channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overhead. the dma controller includes an m2m transfer fea- ture allowing block moves of data from one memory address space to another with minimum of program effort and time. an m2m software trigger capability is provided. the dma controlle r can also fill a block of memory with data from a single location. the dma controller?s m2m channels can also be used in m2p/p2m mode. a set of external handshake signals, dreq, dack and tc/deot are provided for each of two m2m channels. dreq (input) can be programmed edge or level active, and active high or low. the peripheral may hold dreq active for the duration of the block transfers or may assert/deassert on each transfer. dack (output) can be programmed active high or low. dack will assert and return to de- asserted with each read or write, the timing coinciding with noe or nwe from the ebi. tc/deot is a bidirectional signal with programma- ble direction and active polarity. when configured as an output, the dma will assert te rminal count (tc) on the final transfer to coincide with the dack, typically when the byte count has expired. when configured as an input, the peripheral must assert deot concurrent with dreq for the final transfer in the block. transfer is terminated when deot is asserted by the external peripheral or when the byte count expires, whichever occurs first. status bits indicate if the actual byte count is equal to the programmed limit, and if the count was terminated by peripheral asserting deot. terminating the transfer causes a dma interrupt on that channel and rollover to the ?other? buffer if so configured. usb device the features of the usb are: ? compliant with usb 2.0 full speed specification ? provides a high-level interface that removes the usb protocol details from firmware ? compatible with both openhci and intel uhci standards ? supports full-speed (12 mbit/s) functions ? supports suspend and resume signalling. usb host controller the features of the usb host controller are: ? open host controller inte rface specification (open- hci) rev. 1.0 compliant ? universal serial bus specification 2.0 full speed compatible ? supports low speed and high speed usb devices ? root hub has two downstream ports ? dma functionality.
lh7a404 32-bit system-on-chip 26 product data sheet nxp semiconductors color lcd controller the lh7a404?s lcd controller is programmable to support up to 1,024 768, 16-bit color lcd panels. it interfaces directly to stn, color stn, tft, ad-tft, and hr-tft panels. unlike other lcd controllers, the lh7a404?s lcd controller saves an external timing asic by incorporating the timing conversion logic for thin lcd modules such as ad-tft and hr-tft. the color lcd controller features support for: ? up to 1,024 768 resolution ? 16-bit video bus ? 16 bits-per-pixel (bpp) 5:5:5:1 or 5:6:5 direct color or on-chip color palette for 1, 2, 4, and 8 bpp resolution ? stn, color stn, ad-tft, hr-tft, tft panels ? single and dual scan stn panels ? up to 15 gray shades (mono stn) ? up to 3375 colors (color stn) ? up to 64 k-colors ? an on-chip sram frame buffer conserves bus bandwidth and saves active power. ac97 codec controller the ac97 codec controller includes a 5-pin serial interface to an external audio codec. the ac97 link is a bi-directional, fixed rate, serial pulse code modulated (pcm) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit resolution per sample. the ac97 controller contains logic that controls the ac97 link to the audio codec and an interface to the amba apb. its main features include: ? serial-to-parallel conversion for data received from the external codec ? parallel-to-serial conversion for data transmitted to the external codec ? reception/transmission of control and status infor- mation via the amba apb interface ? support for up to 4 simultaneous codec sampling rates with its 4 transmit and 4 receive channels. the transmit and receive paths are buffered with internal fifo memories, allowing data to be stored indepen- dently in both transmit and receive modes. three of the outgoing fifos can be written via either the apb interface or with dma channels 1-3. audio codec in terface (aci) the aci provides: ? a digital serial interface to an off-chip 8-bit codec ? all the necessary clocks and timing pulses to per- form serialization or de-serialization of the data stream to, or from the codec device. the interface supports full duplex operation and the transmit and receive paths are buffered with internal fifo memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. the aci includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip aci clock input (acbitclk). transmit data values are output synchronous with the rising edge of the bit clock output. receive data values are sampled on the falling ed ge of the bit clock output. the start of a data frame is indicated by a synchroniza- tion output signal that is coincident with the bit clock. pulse width modulator (pwm) the pulse width modulator features: ? configurable dual output ? separate input clocks for each pwm output ? 16-bit resolution ? programmable synchronous mode support allows external input to start pwm ? programmable pulse width (duty cycle), interval (frequency), and polarity ? static programming: when the pwm is stopped ? dynamic programming: when the pwm is running ? updates duty cycle, frequency, and polarity at end of a pwm cycle the pwm is a configurable dual-output, dual-clock- input amba slave module, and connects to the apb. synchronous serial port (ssp) the ssp is a master-only interface fo r synchro- nous serial communication with peripheral devices that have either motorola spi, national semicon- ductor microwire, or texas instruments synchronous serial interfaces. the ssp performs serial-to-parallel conversion on data received from a peripheral. the transmit and receive paths are buffered with internal fifo memories allowing up to eight 16-bit values to be stored indepen- dently in both transmit and receive modes. serial data is transmitted on ssptxd and received on ssprxd. the lh7a404 ssp includes a programmable bit rate clock divider and prescaler to generate the serial output clock sclk from the input clock sspclk. bit rates are supported to 2 mhz and beyond , subject to choice of frequency for sspclk; the maximum bit rate will usu- ally be determined by peripheral device?s capability.
32-bit system-on-chip lh7a404 product data sheet 27 nxp semiconductors uart/irda the lh7a404 contains three uarts; uart1, uart2, and uart3. the uart performs: ? serial-to-parallel conversion on data received from the peripheral device ? parallel-to-serial conversion on data transmitted to the peripheral device. the transmit and receive paths can both be routed through the dma separately or simultaneously, and are buffered with internal fifo memories. this allows up to 16 bytes to be stored independently in both transmit and receive modes. the uart can generate: ? four individually maskable interrupts from the receive, transmit, and modem status logic blocks ? a single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. if a framing, parity or break error occurs during reception, the appropriate error bit is set and stored in the fifo. if an overrun condition occurs, the overrun register bit is set immediately and the fifo data is pre- vented from being overwritten. uart1 also supports irda 1.0 (15.2 kbit/s). the modem status input signals clear to send (cts), data carrier detect (dcd) and data set ready (dsr) are supported on uart2 and uart3. timers the lh7a404 includes three programmable timers. each of the timers can operate in two modes: free run- ning and pre-scale. the timers are programmed using four registers; load, value, control, and clear. two identical timers, timer 1 (tc1) and timer 2 (tc2), use clock sources of either 508 khz or 2 khz. the clock source and mode are selectable by writing to the appropriate bits in the system control register. each timer has a 16-bit read/write data register and a control register. the timer is imm ediately loaded with the value written to the data register. this value is then decre- mented on the next active clock edge to arrive after the write. when the timer underflow s, it immediately asserts its appropriate interrupt. timer 3 (tc3) has the same basic operation, but is clocked from a single 7.3728 mhz source. once the timer has been enabled and written to, it decrements on the next rising edge of the 7.3728 mhz clock after the data register has been updated. free-running mode in free-running mode, the timer wraps around to 0xffff when it underflows and continues counting down. pre-scale mode in pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. this mode can be used to produce a pro- grammable frequency to drive the buzzer or generate a periodic interrupt. real time clock (rtc) the rtc provides a basic alarm function or long time-base counter. this is achieved by generating an interrupt signal after counting for a programmed num- ber of cycles of a real-time clock input. counting in one- second intervals is achieved by use of a 1 hz clock input to the rtc. keyboard and mouse interface (kmi) the keyboard and mouse interface has the following features: ? ibm ps/2 or at-compatible keyboard or mouse interface ? half-duplex, bidirectional synchronous serial inter- face using open-drain outputs for clock and data. ? programmable 4-bit reference clock divider ? polled or interrupt-driven mode ? separately maskable transmit and receive interrupts ? single combined interrupt output ? odd parity generation and checking ? register bits for override of keyboard clock and data lines. additional test registers and modes are implemented for functional verification and manufacturing test. a/d converter with br ownout detector and touch screen controller the lh7a404 includes an a/d converter (adc) with integrated touch screen controller (tsc) and brown- out detector. the tsc is a complete interface to a touch screen for portable personal devices. it com- bines the front-end biasing and control circuitry with a/d conversion, reference generation, and digital inter- face functions to completely replace external ics used to implement this interface. the adc features: ? a 10-bit a/d converter with integrated sample-and- hold, fully differential, high impedance signal and ref- erence inputs ? active matrix for bias and control circuits necessary for connection to external 4-, 5-, 7-, and 8-wire touch panels, including pen pressure implementation
lh7a404 32-bit system-on-chip 28 product data sheet nxp semiconductors ? battery voltage sense in addition to normal direct voltage inputs ? a 9-channel multiplexer for routing user-selected inputs to a/d ? a 16 16 fifo for 10-bit digital output of a/d ? a pen-down sensor to generate interrupts to the host ? low-power circuitry and power control modes to minimize on-chip power dissipation ? conversion automation for flexibility while minimizing cpu management and interrupt overhead ? a brownout detector with separate interrupt battery monitor interface (bmi) the bmi is a serial communication interface speci- fied for two types of battery monitors/gas gauges. the first type employs a single wire interface. the second interface employs a two-wire multi-master bus, imple- menting the smart battery system specification. if both interfaces are enabled at the same time, the single wire interface has priority. single wire interface the single wire interface performs: ? serial-to-parallel conversion on data received from the peripheral device ? parallel-to-serial conversion on data transmitted to the peripheral device ? data packet coding/decoding on data transfers (incorporating start/data/stop data packets) the single wire interface uses a command-based protocol in which the host initiates a data transfer by sending a writedata/command word to the battery monitor. smart battery interface the smart battery interface performs: ? serial-to-parallel conversion on data received from the peripheral device ? parallel-to-serial conversion of data transmitted to the peripheral device. the smart battery interface uses a two-wire multi- master bus (the smbus), al lowing multiple bus masters to be connected to it. a master device initiates a bus transfer and provides the clock signals. a slave device can receive data provided by the master or it can pro- vide data to the master. since more than one device may attempt to take control of the bus as a master, smbus provides an arbitration mechanism by relying on the wired-and connection of all smbus interfaces to the smbus. dc-to-dc converter the features of the dc-dc converter interface are: ? dual-drive pwm outputs with independent closed loop feedback ? software programmable configuration of one of 8 output frequencies (each being a fixed division of the input clock). ? software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. ? hardware-configured output polarity (for positive or negative voltage generation) during power-on reset via the polarity select inputs ? dynamically switched pwm outputs to one of a pair of preprogrammed frequency/duty cycle combina- tions via external pins. watchdog timer (wdt) the watchdog timer provides hardware protection against malfunctions. it is a programmable timer that is reset by software at regular intervals. failure to reset the timer will cause an fiq in terrupt. failure to service the fiq interrupt generates a system reset. features of the wdt: ? timing derived from the system clock ? 16 programmable time-out periods: 2 16 through 2 31 clock cycles ? generates a system reset (resets lh7a404) or a fiq interrupt whenever a time-out period is reached ? software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes ? protection mechanism guards against interrupt- service-failure: ? the first wdt time-out triggers fiq and asserts nwdfiq status flag ? if fiq service routine fails to clear nwdfiq, then the next wdt time-out triggers a system reset. general purpose i/o (gpio) the gpio has eight ports, each with a data register and a data direction register. it also has added regis- ters including keyboard scan, pinmux, gpio inter- rupt enable, intype1/2, gpiofeoi and pghcon. the data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the gpio pins. the gpio interrupt enab le, intype[2:1], and the gpiofeoi registers control edge-triggered interrupts on port f. the pinmux register controls which signals are from port d and port e when they are set as out- puts, while the pghcon controls the operations of port g and port h.
32-bit system-on-chip lh7a404 product data sheet 29 nxp semiconductors electrical specifications important: the lh7a404 is an electrostatic discharge (esd) sensitive devic e. esd protection circuitry in ternal to the lh7a404 has been added to reduce esd susceptibility. appropriate esd precauti ons are still requir ed during handling to prevent degradation or failure due to high electrosta tic discharges. system design practices should be evaluated to prevent lh7a404 esd voltages from exceeding the maximum rated volt age as specified in this data sheet. absolute maximum ratings note: these stress ratings are only for transient c onditions. operation at or beyond absolute maximum rating conditions may affect reli ability and cause permane nt damage to the device. recommended operating condi tions for lh7a404-n0e-000 -xx/lh7a404-n0f-000-xx notes: 1. core voltage should never exceed i/o voltage after init ial power up. see ?power supply sequencing? on page 31. 2. many of the peripherals do not operate prope rly at clock speeds other than 14.7456 mhz. some (such as usb) function only at 14.7456 mhz. parameter minimum maximum dc core supply voltage (vddc) ? 0.3 v 2.4 v dc i/o supply voltage (vdd) ? 0.3 v 4.6 v dc analog supply voltage (vdda) ? 0.3 v 2.4 v dc analog supply voltage (vddad) ? 0.3 v 4.6 v 5 v tolerant digital input pin voltage ? 0.5 v 5.5 v esd, human body model (analog pins an0 - an9 rated at 500 v) 2 kv esd, charged device model 1 kv storage temperature ? 55c 125c parameter minimum typical maximum notes dc core supply voltage (vddc) 1.71 v 1.8 v 1.89 v 1 dc i/o supply voltage (vdd) 3.0 v 3.3 v 3.6 v dc analog supply voltage (vdda) 1.71 v 1.8 v 1.89 v dc a/d and tsc supply voltage (vddad) 3.0 v 3.3 v 3.6 v clock frequency 10 mhz 200 mhz bus clock frequency 100 mhz external clock input (xtalin) 14 mhz 14.7456 mhz 20 mhz 2 external clock input (xtalin) voltage 1.71 v 1.8 v 1.89 v operating temperature ? 40c 25c +85c
lh7a404 32-bit system-on-chip 30 product data sheet nxp semiconductors recommended operating co nditions for lh7a404-n0 e-092-xx/lh7a404-n0f-092-xx notes: 1. core voltage should never exceed i/o voltage after in itial power up. see ?power supply sequencing? on page 31. 2. many blocks do not operate properly at speeds other than 14.7456 mhz. some (such as usb) function only at 14.7456 mhz. note: * lh7a404-n0e-000-xx and lh7a404-n0f-000- xx only. table 8 is representa tive of a typical device. guaranteed values are in the re commended operating conditions table. parameter minimum typical maximum notes dc core supply voltage (vddc) 2.0 v 2.1 v 2.2 v 1 dc i/o supply voltage (vdd) 3.14 v 3.3 v 3.6 v dc analog supply voltage (vdda) 2.0 v 2.1 v 2.2 v dc a/d and tsc supply voltage (vddad) 3.0 v 3.3 v 3.6 v clock frequency 10 mhz 266 mhz bus clock frequency 133 mhz external clock input (xtalin) 14 mhz 14.7456 mhz 20 mhz 2 external clock input (xtalin) voltage 1.71 v 1.8 v 1.89 v operating temperature ? 40c 25c +85c table 8. clock frequency vs. voltages (vdd) vs. temperature* parameter 1.71 v 1.80 v 1.89 v 25c clock frequency (fclk) 213 mhz 227 mhz 253 mhz clock period (1/fclk) 4.69 ns 4.41 ns 3.95 ns 70c clock frequency (fclk) 205 mhz 220 mhz 236 mhz clock period (1/fclk) 4.88 ns 4.46 ns 2.36 ns 85c clock frequency (fclk) 200 mhz 212 mhz 232 mhz clock period (1/fclk) 5.00 ns 4.72 ns 4.24 ns figure 5. temperature/voltage/speed chart (lh7a404-n0e-000-xx and lh7a404-n0f-000-xx only) lh7a404-182 frequency (mhz) 250 255 245 240 235 230 225 220 215 210 205 200 25 35 45 55 temp ( c) 65 75 85 1.89 v (+5%) 1.80 v 1.71 v (-5%)
32-bit system-on-chip lh7a404 product data sheet 31 nxp semiconductors power supply sequencing nxp recommends that the 1.8 v power supply be energized before the 3.3 v supply. if this is not possi- ble, the 1.8 v supply may not lag the 3.3 v supply by more than 100 ? s. if longer delay time is needed, it is recommended that the voltage difference between the two power supplies be within 1.5 v during power supply ramp up. to avoid a potential latchup condition, voltage should be applied to input pins only after the device is powered-on as described above. dc/ac specifications the dc and ac specifications appears in the table below. parameters apply to all part numbers except where noted. dc specifications notes: 1. output drive 5 can sink 20 ma of current, but sources 12 ma of current. 2. current consumption until oscillators are stabilized. 3. see ?current consumption by operating mode?, page 34 for operating conditions. 4. both oscillators running, lcd active; all ot her peripheral s stopped. 5. 32 khz oscillator running; all other peripherals stopped. symbol parameter min. typ. max. unit conditions note vih cmos/schmitt trigger input high voltage 2.0 v vil cmos/schmitt trigge r input low voltage 0.8 v vhst schmitt trigger hysteresis 0.25 v vil to vih voh cmos output high voltage, output drive 1 2.6 v ioh = -2 ma output drive 2 2.6 v ioh = -4 ma output drive 3 2.6 v ioh = -8 ma output drive 4 and 5 2.6 v ioh = -12 ma 1 vol cmos output low voltage, output drive 1 0.4 v iol = 2 ma output drive 2 0.4 v iol = 4 ma output drive 3 0.4 v iol = 8 ma output drive 4 0.4 v iol = 12 ma output drive 5 0.4 v iol = 20 ma 1 iin input leakage current -10 10 ? a vin = vdd or gnd input leakage current, with pullup resistors -95 10 ? a ioz output tri-state leakage current -10 10 ? a vout = vdd or gnd istartup startup current 50 ? a2 cin input capacitance 4 pf cout output capacitance 4 pf lh7a404-n0e-000-xx and lh7a404-n0f-000-xx only iactive active current (operating current) 147 238 ma 3 ihalt halt current 41 45 ma 4 istandby standby current 70 ? a5 lh7a404-n0e-092-xx and lh7a404-n0f-092-xx only iactive active current (operating current) 228 370 ma 3 ihalt halt current 60 ma 4 ihalt standby current 200 ? a5
lh7a404 32-bit system-on-chip 32 product data sheet nxp semiconductors analog-to-digital converter electrical characteristics table 9 shows the derated specifications for extended temperature operation. see figure 6 for the adc transfer characteristics. notes: 1. the analog section of the adc takes 16 a2dclk cycles per conversion, plus 1 a2dclk cycles to be made available in the pclk domain. an additional 3 pclk cycles are required be fore being available on the apb. 2. data out = 0000000000 when the analog input equals the negative reference. data out = 1111111111 when the analog input equals the positive reference. 3. guaranteed monotonic. 4. inl calculated as deviation from ?best fit? line af ter subtracting offset/gain errors over the center 90 % of full scale output range. 5. dc voltage error for the transition voltage from code 511 (0x1ff) to 512 (0x200) 6. the internal voltage reference is driven to nominal va lue vref = 2.0 v. using the reference multiplexer, alternative low impedance (rs < 500) voltages can be selected as reference voltages. the range of voltages allowed are specified above. 7. the analog input pins can be driven anywhere between the power supply rails. if the voltage at the input to the adc exceeds vref+ or is below vref-, the a/d result will saturate appropriately at positive or negative full scale. tr ying to pull the analog input pins above or below the power supply rails will cause protection diodes to be forward- biased, resulting in large current s ource/sink and possible damage to the adc. 8. bandgap and other low-bandwidth circuitry operating. all other adc blocks shut down. table 9. adc electrical characteristics parameter min. typ. max. units notes a/d resolution 10 10 bits throughput conversion 17 clk cycles 1 acquisition time 3 clk cycles data format binary 2 clk frequency 500 5,000 ns differential non-linearity (dnl) -0.99 +4.5 lsb 3 integral non-linearity (inl) -4.5 +4.5 lsb 4 offset error +35 +50 mv 5 gain error -4.0 4.0 lsb reference voltage output 1.85 2.0 2.15 v vref- vssa vssa (vref+) -1.0 v 6 vref+ (vref-) +1.0 vref vddad v 6 crosstalk between channels -60 db analog input voltage range 0 vddad v 7 analog input current 5 ? a reference input current 5 ? a analog input capacitance 15 pf operating supply voltage 3.0 3.6 v operating current, vddad 590 1000 ? a standby current, vddad 180 ? a8 stop current, vddad 1 ? a brownout trip point (falling point) 2.36 2.63 2.9 v brownout hysteresis 120 mv operating temperature ? 40 85 c
32-bit system-on-chip lh7a404 product data sheet 33 nxp semiconductors ac test conditions figure 6. adc transfer characteristics parameter rating unit dc i/o supply voltage (vdd) 3.0 to 3.6 v dc core supply voltage (vddc) 1.7 to 1.9 v input pulse levels vss to 3 v input rise and fall times 2 ns input and output timing reference levels vdd/2 v 1015 1 2 3 4 5 6 7 8 9 1018 1019 1020 1021 1022 1023 1024 1016 1017 1018 1019 lh7a404-154 1020 1021 1022 1023 1024 123456789 integral non-linearity actual transfer curve ideal transfer curve center of a step of the actual transfer curve offset error offset error lsb dnl gain error
lh7a404 32-bit system-on-chip 34 product data sheet nxp semiconductors current consumption by operating mode current consumption can depend on a number of parameters. to make these data more usable, the values presented in table 11 were derived under the conditions described here. maximum specified value the values specified in the maximum column were determined using these operating characteristics: ? all ip blocks either operating or enabled at maximum frequency and size configuration ? core operating at maximum power configuration ? all voltages at maximum specified values ? nominal specified ambient temperature. typical the values in the typical column were determined using a ?typical? application under ?typical? environmental conditions and the following operating characteristics: ? linux operating system running from sdram ? uart and ac97 peripherals operating; all other peripherals as needed by the os ? lcd enabled with 320 240 16-bit color, 60 hz refresh rate, data in sdram ? i/o loads at nominal ? cache enabled ? fclk = 200; hclk = 100; pclk = 50 mhz ? all voltages at typical values ? nominal case temperature. peripheral current consumption in addition to the modal current consumption, table 10 shows the typical current consumption for each of the on-board peripheral blocks. the values were determined with the peripheral clock running at 200 mhz, typical conditions, and no i/o loads. this current is supplied by the 1.8 v power supply. notes: 1. fclk = 200 mhz pertains to lh7a404-n0e-000-xx and lh7a404-n0f-000-xx 2. fclk = 266 mhz pertains to lh7a404-n0e-092-xx and lh7a404-n0f-092-xx. table 10. peripheral current consumption peripheral typical units ac97 1.3 ma uart (each) 1.0 ma rtc 0.005 ma timers (each) 0.1 ma lcd (+i/o) 5.4 (+1.0) ma mmc 0.6 ma sci 23 ma pwm (each) 45 ? a bmi-swi 1.0 ma bmi-sbus 1.0 ma sdram (+i/o) 1.5 (+14.8) ma usb device (+pll) 5.6 (+3.3) ma aci 0.8 ma vic 610 ? a kmi 38 ? a usb host 715 ? a adc/tsc 590 ? a table 11. current consumption by mode symbol parameter fclk = 200 mhz (typ.) fclk = 266 mhz (typ.) units run mode icore core current 132 199 ma iio i/o current 15 29 ma halt mode (all peripherals disabled) icore core current 40 58 ma iio i/o current 1 2 ma standby mode (typical conditions only) icore core current 66 200 ? a iio i/o current 4 4 ? a
32-bit system-on-chip lh7a404 product data sheet 35 nxp semiconductors ac specifications all signals described in table 12 relate to transi- tions following an internal reference clock signal. the illustration in figure 7 represents all cases of these sets of measurement parameters. the reference clock signals in this design are: ? hclk, internal system bus clock (?c? in timing data) ? pclk, the peripheral bus clock ? sspclk, the synchronous serial port clock ? uartclk, the uart interface clock ? lcddclk, the lcd data clock from the lcd controller ? acbitclk, the ac97 and aci clock ? sclk, the synchronous memory clock. all signal transitions are measured from the 50 % point of the clock to the 50 % point of the signal. for outputs from the lh7a404, tovxxx (e.g. tova) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. maximum requirements for tovxxx are shown in table 12. the signal tohxxx (e.g. toha) represents the amount of time the output must be held valid after the rising edge of the reference clock signal. minimum requirements for tohxxx are listed in table 12. for inputs, tisxxx (e.g. tisd) represents the amount of setup time the input signal must be valid after a valid address bus, or rising edge of the peripheral clock. maximum requirements for tisxxx are shown in table 12. the signal tihxxx (e.g. tihd) represents the amount of time the output must be held valid following the rising edge of the reference clock signal. minimum requirements are shown in table 12. figure 7. lh7a404 signal timing reference clock output signal (o) input signal (i) tovxxx tohxxx tisxxx tihxxx lh7a404-9
lh7a404 32-bit system-on-chip 36 product data sheet nxp semiconductors table 12. ac signal characteristics signal type load symbol min. max. description notes asynchronous memory interface signals (+ [wait states hclk period]) a[27:0] output 50 pf trc 4 thclk ? 7.0 ns 4 thclk + 7.5 ns read cycle time 1 output 50 pf twc 4 thclk ? 7.0 ns 4 thclk + 7.5 ns write cycle time 1 ? ? tws thclk ns thclk ns wait state width 1 d[31:0] output 50 pf tdvwe thclk ? 6.0 ns thclk ? 2.0 ns data valid to write edge (nwe invalid) 1 tdhwe thclk ? 7.0 ns thclk + 2.0 ns data hold after write edge (nwe invalid) 1 tdvbe thclk ? 5.0 ns thclk ? 1.0 ns data valid to nble invalid 1 tdhbe thclk ? 7.0 ns thclk + 3.0 ns data hold after nble invalid 1 input ? tdscs 15 ns ? data setup to ncsx invalid 1 tdhcs 0 ns ? data hold to ncsx invalid 1 tdsoe 15 ns ? data setup to noe invalid 1 tdhoe 0 ns ? data hold to noe invalid 1 tdsbe 15 ns ? data setup to nble invalid 1 tdhbe 0 ns ? data hold to nble invalid 1 ncs[7:0] output 50 pf tcs 2 thclk ? 3.0 ns 2 thclk + 3.0 ns ncsx width 1 tavcs thclk ? 4.0 ns thclk address valid to ncsx valid 1 tahcs thclk thclk + 4.5 ns address hold after ncsx invalid 1 nwe output 50 pf twe thclk ? 2.0 ns thclk + 1.0 ns nwe width 1 tavwe thclk ? 4.0 ns thclk ns address valid to nwe valid 1 tcshwe thclk ? 1.0 ns thclk + 2.0 ns ncsx hold after nwe invalid 1 noe output 50 pf toe 2 thclk ? 3.0 ns 2 thclk + 3.0 ns noe width 1 tavoe thclk ? 4.0 ns thclk address valid to noe valid 1 tahoe thclk thclk + 4.5 ns address hold after noe invalid 1 nble (write) output 50 pf tbew thclk ? 5.0 ns thclk nble width 1 tavbe thclk ? 2.0 ns thclk address valid to nble valid 1 tcshbe thclk thclk + 3.0 ns ncsx hold after nble invalid 1 nble (read) output 50 pf tber 2 thclk ? 5.0 ns 2 thclk + 3.0 ns nble width 1 tavbe thclk ? 2.0 ns thclk address valid to nble valid 1 tahbe thclk thclk + 4.5 ns address hold after nble invalid 1 synchronous memory interface signals (?-092? parts / ?-000? parts) sa[13:0] output 50 pf tova ? 5.5/7.5 ns address valid 2 toha 1.5/1.5 ns ? address hold 2 a[17:16]/ sb[1:0] output 50 pf tovb ? 5.5/7.5 ns bank select valid 2 d[31:0] output 50 pf tohd 1.5ns ? data hold 2 tovd 2 ns 5.5/7.5 ns data valid 2 input ? tisd 1.5/2.5 ns ? data setup 2 tihd 1.0/1.5 ns ? data hold 2 ncas output 50 pf tovca 2 ns 5.5/7.5 ns cas valid 2 tohca 1.5/2 ns ? cas hold 2 nras output 50 pf tovra 2 ns 5.5/7.5 ns ras valid 2 tohra 1.5/2 ns ? ras hold 2 nswe output 50 pf tovsdw 2 ns 5.5/7.5 ns write enable valid 2 tohsdw 1.5/2 ns ? write enable hold 2 scke[1:0] output 50 pf tovc0 2 ns 5.5/7.5 ns clock enable valid 2 dqm[3:0] output 50 pf tovdq 2 ns 5.5/7.5 ns data mask valid 2 nscs[3:0] output 50 pf tovsc 2 ns 5.5/7.5 ns synchronous chip select valid 2 tohsc 1.5/2 ns ? synchronous chip select hold 2 pcmcia interface signals (+ [wait states hclk period]) npcreg output 50 pf tovdreg ? thclk + 5 ns nreg valid tohdreg 4 thclk ? 5 ns ? nreg hold
32-bit system-on-chip lh7a404 product data sheet 37 nxp semiconductors notes: 1. register bcrx:wst1 = 0b000 2. the ?x/x? in the min./max. indicates (lh7a404-n0e-092-xx and h7a404-n0f-092-xx)/ (lh7a404-n0e-000-xx and lh7a404- n0f-000-xx), respectively. 3. ?tcyc? is the period of one mmc clock 4. ?tcyc? is the period of one ac97 clock 5. ?nc? in the min./max. columns indicates the number of system clock (hclk) periods after valid address 6. for output drive strength spec ifications, refer to table 2 d[31:0] output 50 pf tovd ? thclk + 5 ns data valid tohd 4 thclk ? 6 ns ? data hold input ? tisd ? thclk - 10 ns data setup time tihd 4 thclk ? 5 ns ? data hold time npcce1 output 50 pf tovce1 ? thclk + 5 ns chip enable 1 valid tohce1 4 thclk ? 5 ns ? chip enable 1 hold npcce2 output 50 pf tovce2 ? thclk + 5 ns chip enable 2 valid tohce2 4 thclk ? 5 ns ? chip enable 2 hold npcoe output 50 pf tovoe ? thclk + 5 ns output enable valid tohoe 3 thclk ? 5 ns ? output enable hold npcwe output 50 pf tovwe ? n thclk + 5 ns write enable valid tohwe 3 thclk ? 5 ns ? write enable hold pcdir output 50 pf tovpcd ? thclk + 5 ns card direction valid tohpcd 4 thclk ? 5 ns ? card direction hold mmc interface signals mmccmd output 50 pf tovcmd ? ?tcyc ? 3 ns mmc command valid 3 tohcmd ?tcyc + 3 ns ? mmc command hold 3 mmcdata output 50 pf tovdat ? ?tcyc ? 3 ns mmc data valid 3 tohdat ?tcyc + 3 ns ? mmc data hold 3 mmcdata input ? tisdat 5 ns ? mmc data setup tihdat 5 ns ? mmc data hold mmccmd input ? tiscmd 5 ns ? mmc command setup tihcmd 5 ns ? mmc command hold ac97 interface signals acout output 50 pf tovac97 ? ?tcyc ? 10 ns ac97 output valid 4 tohac97 ?tcyc + 10 ns ? ac97 output hold 4 acin input ? tisac97 2.5 ns ? ac97 input setup tihac97 2.5 ns ? ac97 input hold acsync output 50 pf tovac97 ? ?tcyc ? 10 ns ac97 synchronization valid 4 tohac97 ?tcyc + 10 ns ? ac97 synchronization hold 4 synchronous serial port (ssp) sspfrm output 50 pf tovfrm ? 10 ns ssp frame output valid tohfrm 5 ns ? ssp frame output hold ssptx output 50 pf tovtx 10 ns ssp transmit valid tohtx 5 ns ? ssp transmit hold ssprx input ? tisrx 14 ns ? ssp receive setup tihrx 14 ns ? ssp receive hold sspclk output 50 pf tclk 8.819 ms 271 ns ssp clock period audio codec interface (aci) acout output 50 pf tovd ? 15 ns acout delay from rising clock edge tohd 10 ns ? acout hold acin input tis 10 ns ? acin setup tih 2.5 ns ? acin hold color lcd controller lcdvd [17:0] output 50 pf tov ? 3 ns lcd data clock to data valid table 12. ac signal characteristics (cont?d) signal type load symbol min. max. description notes
lh7a404 32-bit system-on-chip 38 product data sheet nxp semiconductors smc waveforms figure 8 and figure 9 show waveforms and timing for an external asynchronous memory write. figure 10 and figure 11 show the waveforms and timing for an external asynchronous memory read. figure 8. external asynchronous memory write, zero wait states (bcrx:wst1 = 0b000) hclk a[27:0] twc valid address valid data tdvwe, tdvbe tdhwe, tdhbe lh7a404-10 01 2 34 tcs ncs valid nwe valid nble valid tavcs tahcs twe tcshwe tavwe tbew tcshbe tavbe d[31:0] ncsx nwe nble write edge
32-bit system-on-chip lh7a404 product data sheet 39 nxp semiconductors figure 9. external asynchronous memory write, four wait states (bcrx:wst1 = 0b100) lh7a404-189 a[27:0] hclk 0 wait state wait state 1 wait state 2 wait state 3 wait state 4 d[31:0] ncsx nwe nble write edge 8 7 6 5 4 3 2 1 0 ncsx valid nwe valid nble valid tws tws tws tws valid address valid data
lh7a404 32-bit system-on-chip 40 product data sheet nxp semiconductors figure 10. external asynchronous memory read, zero wait states (bcrx:wst1 = 0b000) hclk a[27:0] trc tahcs, tahoe, tahbe tdhcs tdhbe tdhoe valid data valid address data latched here lh7a404-190 01 234 tavcs tdscs tdsbe tcs tber tdsoe toe tavoe tavbe d[31:0] ncsx noe nble ncs valid noe valid nble valid
32-bit system-on-chip lh7a404 product data sheet 41 nxp semiconductors figure 11. external asynchronous memory read, four wait states (bcrx:wst1 = 0b100) lh7a404-12 10 9 8 7 6 5 4 3 2 1 0 a[27:0] hclk valid address d[31:0] ncs[3:0, cs[7:6] noe valid data nble 0 wait state, data would be latched here tws 4 wait states, data latched here wait state 1 wait state 2 wait state 3 wait state 4 ncsx valid noe valid nble valid tws tws tws
lh7a404 32-bit system-on-chip 42 product data sheet nxp semiconductors timing for nwait signalling in addition to being able to program the number of wait states, the smc also can use nwait signalling to extend transactions. when the nwait input is asserted, the current transaction is he ld in suspense until nwait is released, allowing slow memory or memory-mapped peripherals time to complete the action. figure 12 through figure 17 illustrate nwait timing using different wst register settings and circumstances. notes: 1. the timing relationship is s pecified as a cycle-based timing. variations caused by clock jitter, power rail noise, and i/o cond- tioning will cause thes e timings to vary no minally. it is recom- mended that designers add a small margin to avoid possible corner-case conditions. 2. the bank configuration regist er (bcrx:wst1) must have read wait states set to a minimum of 2. 3. the number of hclk periods that nwait lags assertion of ncsx must be added to the minimum value for bcrx:wst1. for exam- ple, if nwait lags ncsx by 3 hclk periods, the minimum setting of bcrx:wst1 is 2 + 3, or a tota l of 5 as the minimum value for bcrx:wst1. 4. no nwait delay cycles are added for any nwait assertions that occur prior to the beginning of the wsd-2 delay. these nwait assertions are ignored. 5. once the wsd-2 delay begins, one hclk cycle is added to the transaction each time nwait is sampled and queued (sq-x). the nwait cycles begin being added after the wait state countdown reaches wsd-0. 6. once nwait is sampled high (de-asserted), the current memory transaction is queued to complete. 7. since static and dynamic memory cannot be accessed at the same time, prolonged extension of an smc transaction by either wait states or nwait delays can cause refresh failure for the sdram, and may cause sdram data loss. figure 12. nwait read sequence (bcrx:wst1 = 2); minimum wait state example parameter description min. max. unit 1 tda_ncs(x)_nwait delay from ncs(x) assertion to nwait assertion 0 29 hclk periods tdd_nwait_ncs(x) delay from nwait deassert ion to ncs(x) deassertion 4 hclk periods tdd_nwait_noe delay from nwait deasse rtion to noe deassertion 4 hclk periods ta_nwait assertion time of nwait 2 hclk periods tda_ncs(x)_nwait hclk ncs(x) noe nwait notes: sq: nwait sampled and queued si: nwait sampled and ignored ta_nwait sq-4 sq-3 sq-2 sq-1 sq-0 tdd_nwait_ncs(x) tdd_nwait_noe lh7a404-203 wsd-2 delay wsd-1 delay wsd-0 delay sq-4 nwait delay sq-3 nwait delay sq-2 nwait delay sq-1 nwait delay sq-0 nwait delay end cycle transaction sequence
32-bit system-on-chip lh7a404 product data sheet 43 nxp semiconductors figure 13. nwait read sequence (bcrx:wst1 = 4); ignored and queued nwait delays figure 14. nwait read sequence (bcrx:wst1 = 4); nwait has no effect on current transaction wsd-4 delay wsd-3 delay wsd-2 delay wsd-1 delay wsd-0 delay sq-4 nwait delay sq-3 nwait delay sq-2 nwait delay sq-1 nwait delay sq-0 nwait delay end cycle tdd_nwait_ncs(x) tdd_nwait_noe) ta_nwait si si sq-4 sq-3 sq-2 sq-1 sq-0 ncs(x) noe nwait hclk transaction sequence notes: sq: nwait sampled and queued si: nwait sampled and ignored tda_ncs(x)_nwait lh7a404-204 wsd-4 delay wsd-3 delay wsd-2 delay wsd-1 delay wsd-0 delay end cycle si si ncs(x) hclk noe nwait transaction sequence notes: sq: nwait sampled and queued si: nwait sampled and ignored lh7a404-205 tda_ncs(x)_nwait ta_nwait
lh7a404 32-bit system-on-chip 44 product data sheet nxp semiconductors notes: 1. the timing relationship is specif ied as a cycle-based timing. vari ations caused by clock jitter, power rail noise, and i/o condtioni ng will cause these timings to va ry nominally. it is recommended that designers add a small margin to avoi d possible corner -case conditions. 2. the bank configuration register (bcrx:wst1) must have write wait states set to a minimum of 2. 3. the number of hclk periods that nwait lags as sertion of ncsx must be added to the minimum value for bcrx:wst1. for example, if nwait lags ncsx by 3 hclk periods, the minimum setting of bcrx:wst1 is 2 + 3, or a total of 5 as the minimum value for bcrx:wst1. 4. no nwait delay cycles are added for any nwait assertions that occur prior to the beginning of the wsd-2 delay. these nwait assertions are ignored. 5. once the wsd-2 delay begins, one hclk cycle is added to the transaction each time nwait is sampled and queued (sq-x). the nwait cycles begin being added after the wa it state countdown reaches wsd-0. 6. once nwait is sampled high (de-asserted), th e current memory transaction is queued to complete. 7. since static and dynamic memory cannot be a ccessed at the same time, prolonged extension of an smc transaction by either wait states or nwai t delays can cause refresh failure for the sdram, and may cause sdram data loss. figure 15. nwait write sequence (bcrx:wst1 = 2); minimum wait state example parameter description min. max. unit 1 tida_ncs(x)_nwait delay from ncs(x) assertion to nwait assertion 0 29 hclk periods tdd_nwait_ncs(x) delay from nwait deassert ion to ncs(x) deassertion 4 hclk periods tdd_nwait_nwe delay from nwait deasse rtion to nwe deassertion 3 hclk periods ta_nwait assertion time of nwait 2 hclk periods tda_ncs(x)_nwait hclk ncs(x) nwe nwait notes: sq: nwait sampled and queued si: nwait sampled and ignored ta_nwait sq-4 sq-3 sq-2 sq-1 sq-0 tdd_nwait_ncs(x) tdd_nwait_nwe lh7a404-206 wsd-2 delay wsd-1 delay wsd-0 delay sq-4 nwait delay sq-3 nwait delay sq-2 nwait delay sq-1 nwait delay sq-0 nwait delay end cycle transaction sequence
32-bit system-on-chip lh7a404 product data sheet 45 nxp semiconductors figure 16. nwait write sequence (bcrx:wst1 = 4); ignored and queued nwait delays wsd-4 delay wsd-3 delay wsd2 delay wsd-1 delay wsd-0 delay sq-4 nwait delay sq-3 nwait delay sq-2 nwait delay sq-1 nwait delay sq-0 nwait delay end cycle tdd_nwait_ncs(x) tdd_nwait_nwe ta_nwait si si sq-4 sq-3 sq-2 sq-1 sq-0 ncs(x) nwe nwait hclk transaction sequence notes: sq: nwait sampled and queued si: nwait sampled and ignored tda_ncs(x)_nwait lh7a404-207
lh7a404 32-bit system-on-chip 46 product data sheet nxp semiconductors figure 17. nwait write sequence (bcrx:wst1 = 4); nwait has no ef fect on curren t transaction wsd-4 delay wsd-3 delay wsd-2 delay wsd-1 delay wsd-0 delay end cycle si si ncs(x) hclk nwe nwait transaction sequence notes: sq: nwait sampled and queued si: nwait sampled and ignored lh7a404-208 tda_ncs(x)_nwait ta_nwait
32-bit system-on-chip lh7a404 product data sheet 47 nxp semiconductors synchronous memory controller waveforms figure 18 shows the waveform and timing for a syn- chronous burst read (page already open). figure 19 shows the waveform and timing for synchronous mem- ory to activate a bank and write. figure 18. synchronous burst read figure 19. synchronous bank activate and write lh7a404-13 sa[13:0], sbank[1:0] d[31:0] notes: 1. sdramcmd is the combination of nras, ncas, nsdwe, and nsdcsx. 2. tovxxx represents tovra, tovca, tovsdw, or tovsc. 3. tohxxx represents tohra, tohca, tohsdw, or tohsc. 4. ndqm is static low. 5. sdcke is static high. sclk sdramcmd t ovxxx t ovb t ohxxx read bank, column tova tisd tihd data n data n + 1 data n + 2 data n + 3 d[31:0] sclk scke sdramcmd tovc tovxxx tova tohxxx toha notes: 1. sdramcmd is the combination of nras, ncas, nswe, and nscsx. 2. tovxxx represents tovra, tovca, tovsvw, or tovsc. refer to the ac timing table. 3. tohxxx represents tohra, tohca, tohsvw, or tohsc. active write data bank, row bank, column tovd tohd sa[13:0], sb[1:0] lh7a400-24
lh7a404 32-bit system-on-chip 48 product data sheet nxp semiconductors ssp waveforms the synchronous serial port (ssp) supports three data frame formats: ? texas instruments ssi ? motorola spi ? national semiconductor microwire each frame format is between 4 and 16 bits in length, depending upon the programmed data size. each data frame is transmitted beginning with the most significant bit (msb) i. e. ?big endian?. for all three formats, the ssp serial clock is held low (inac- tive) while the ssp is idle. the ssp serial clock tran- sitions only during active transmission of data. the sspfrm signal marks the beginning and end of a frame. figure 20 and figure 21 show texas instruments synchronous serial frame format, figure 22 through figure 29 show the motorola spi format, and figure 30 and figure 31 show national semiconductor?s micro- wire data frame format. for texas instruments ssi format, the sspfrm pin is pulsed prior to each frame?s transmission for one serial clock period beginning at its rising edge. for this frame format, both the ssp and the external slave device drive their output data on the rising edge of the clock and latch data from the other device on the falling edge. see figure 20 and figure 21. figure 20. texas instruments synchronous serial frame format (single transfer) figure 21. texas instruments synchronous serial frame format (continuous transfer) lh7a404-24a sspclk sspfrm msb lsb ssptx/ ssprx 4 to 16 bits tclk tisrx tohfrm tovfrm lh7a404-25 sspclk sspfrm ssptxd/ ssprxd msb lsb 4 to 16 bits
32-bit system-on-chip lh7a404 product data sheet 49 nxp semiconductors for motorola spi, the seri al frame pin (sspfrm) is active low. the spo and sph bits in ssp control register 0 determine sspc lk and sspfrm operation in single and continuous modes. see figures 22 through 29. figure 22. motorola spi frame format (single transfer) with spo = 0 and sph = 0 figure 23. motorola spi frame format (continuous transfer) with spo = 0 and sph = 0 figure 24. motorola spi frame format (single transfer) with spo = 0 and sph = 1 lh7a404-26 sspclk nsspfrm ssprxd msb ssptxd 4 to 16 bits msb lsb lsb q note: q is undefined. lh7a404-27 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb lsb msb msb lh7a404-28 sspclk nsspfrm ssprxd ssptxd note: q is undefined. 4 to 16 bits lsb lsb q q msb msb
lh7a404 32-bit system-on-chip 50 product data sheet nxp semiconductors figure 25. motorola spi frame format (continuous transfer) with spo = 0 and sph = 1 figure 26. motorola spi frame format (continuous transfer) with spo = 1 and sph = 1 figure 27. motorola spi frame format (single transfer) with spo = 1 and sph = 0 lh7a404-29 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb msb lsb msb lh7a404-30 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb msb lsb msb lh7a404-31 sspclk nsspfrm ssprxd ssptxd note: q is undefined. msb msb lsb lsb q 4 to 16 bits
32-bit system-on-chip lh7a404 product data sheet 51 nxp semiconductors figure 28. motorola spi frame format (continuous transfer) with spo = 1 and sph = 0 figure 29. motorola spi frame format (single transfer) with spo = 1 and sph = 1 lh7a404-32 sspclk nsspfrm ssptxd/ ssprxd msb lsb msb lsb 4 to 16 bits lh7a404-33 sspclk nsspfrm ssprxd ssptxd 4 to 16 bits msb msb q lsb lsb q note: q is undefined.
lh7a404 32-bit system-on-chip 52 product data sheet nxp semiconductors for national semiconductor microwire format, the serial frame pin (sspfrm) is active low. both the ssp and external sl ave device drive their output data on the falling edge of the cloc k, and latch data from the other device on the rising edge of the clock. unlike the full-duplex transmission of the other two frame formats, the national semiconducto r microwire format uti- lizes a master-slave messaging technique that oper- ates in half-duplex. when a frame begins in this mode, an 8-bit control message is transmitted to the off-chip slave. during this transmission no incoming data is received by the ssp. after the message ha s been sent, the external slave device decodes the message. after waiting one serial clock period after the last bit of the 8- bit control message was received it responds by return- ing the requested data. the returned data can be 4 to 16 bits in length, making the total frame length between 13 to 25 bits. see figure 30 and figure 31. figure 30. microwire frame format (single transfer) figure 31. microwire frame format (continuous transfers) lh7a404-34 lsb msb 0 lsb msb 8-bit control sspclk nsspfrm ssptxd ssprxd 4 to 16 bits output data lh7a404-35 sspclk nsspfrm ssptxd ssprxd 4 to 16 bits output data 8-bit control msb msb lsb lsb 0 lsb msb
32-bit system-on-chip lh7a404 product data sheet 53 nxp semiconductors figure 32. general ssp timing sspclk (programmable clock phase) sspfrm (programmable frame phase and duration) ssprx ssptx clock phase 1 clock phase 2 bitn output bitn input bitn-1 output bitn-1 input tovtx tisrx tovfrm tohfrm tihrx tohtx tclk lh7a404-199
lh7a404 32-bit system-on-chip 54 product data sheet nxp semiconductors pc card (pcmcia) waveforms figure 33 shows the wa veforms for pcmcia read transactions and figure 34 shows the waveforms and timing for write transactions. figure 35 shows the pre- charge, access, and hold timing relationships. figure 33. pcmcia read transfer tovdreg hclk a[25:0] tovpcd tisd tovoe tohdreg address precharge time (see note 1) access time (see note 1) hold time (see note 1) tohpcd data tihd tohoe tovcex tohcex lh7a404-15 npcreg npccex (see note 2) pcdir d[31:0] npcoe/ npcior notes: 1. precharge time, access time, and hold time are programmable wait-state times. 2. npcce1 0 0 1 1 npcce2 0 1 0 1 transfer type common memory attribute memory i/o none
32-bit system-on-chip lh7a404 product data sheet 55 nxp semiconductors figure 34. pcmcia write transfer figure 35. pcmcia precharge, access, and hold waveform tovdreg hclk a[25:0] tovpcd tovd tovwe tohdreg address precharge time (see note 1) access time (see note 1) hold time (see note 1) tohd tohwe tovcex tohcex lh7a404-16 npcreg npccex (see note 2) pcdir d[15:0] npcwe/ npciow notes: 1. precharge time, access time, and hold time are programmable wait-state times. 2. npcce1 0 0 1 1 npcce2 0 1 0 1 transfer type common memory attribute memory i/o none data lh7a404-194 access precharge npcwe, npcoe, npciow, npcior ncsx hold
lh7a404 32-bit system-on-chip 56 product data sheet nxp semiconductors mmc interface waveforms figure 36 shows the waveforms and timing for an mmc command or data write. figure 37 shows the wave- forms and timing for an mmc command or data read. ac97 interface waveforms figure 38 shows the waveforms and timing for the ac97 interface data setup and hold. figure 36. mmc command/data write figure 37. mmc command/data read figure 38. ac97 data setup and hold tovcmd mmcclk mmccmd mmcdata tohcmd tmmcclk tovdat tohdat lh7a404-19 tiscmd mmcclk mmccmd mmcdata tihcmd tisdat tihdat lh7a404-20 tovac97 acbitclk acout/acsync acin tisac97 tihac97 tohac97 tacbitclk lh7a404-21
32-bit system-on-chip lh7a404 product data sheet 57 nxp semiconductors audio codec inte rface (aci) timing the timing for the audio codec interface are shown in figure 39 and figure 40. transmit data is clocked on the rising edge of acbitclk (whether transmitted by the lh7a404 aci or by t he external codec chip); receive data is clocked on the falling edge. this allows full-speed, full duplex operation. color lcd controller waveforms figure 41 shows the valid output setup time for lcd data. timing diagrams for each clcdc mode are represented in figure 42 through figure 47. figure 39. aci signal timing figure 40. aci data stream figure 41. clcdc valid output data time tovd tohd tis tih acbitclk acsync/acout acin lh7a404-178 lh7a404-153 acbitclk acsync acin acin sampled on falling edge 76 bit 5 4 3 2 1 0 7 6 lcddclk data valid tov lh7a404-198 lcdvd (soc output)
lh7a404 32-bit system-on-chip 58 product data sheet nxp semiconductors figure 42. stn horizontal timing 1 stn horizontal line clcdc clock (internal) timing2: csel timing2: bcd lcdlp (line sync pulse) timing2:ihs lcddclk (panel data clock) timing2:pcd timing2:bcd timing2:ipc timing2:cpl lcdvd (lcd data) (see note 1) notes: 1. the active data lines will vary with the type of stn panel: 4-bit, 8-bit, color or mono. 2. circled numbers are lh7a404 pin numbers. timing0:hsw timing0:hbp d001 d002 d.... one 'line' of lcd data dnnn timing0:hfp horizontal back porch horizontal front porch enumerated in 'lcddclks' enumerated in 'lcddclks' lh7a404-98 lcddclk is suppressed during lcdllp v2 y10 16 (timing0:ppl+1)
32-bit system-on-chip lh7a404 product data sheet 59 nxp semiconductors figure 43. stn vertical timing vdd display-dependent turn-on delay 1 stn frame panel positive high-voltage supply active panel negative high-voltage supply active panel logic active panel data clock active ac bias active back porch enumerated in horizontal 'lines' see 'stn horizontal timing diagram' enumerated in horizontal 'lines' front porch all 'lines' for one frame vss lcdvdden (display enable) lcddclk (panel data clock) lcdtiming2:pcd lcdtiming2: bcd lcdtiming2: ipc lcdenab (ac bias) lcdtiming2:acb lcdtiming2: ioe lcdfp (frame pulse) lcdtiming1: ivs pixel data and horizontal control signals for one frame notes: 1. signal polarities may vary for some displays. 2. circled numbers are lh7a404 pin numbers. lcdtiming1: vbp = 0 lcdtiming1: lpp lcdtiming1: vfp lcdtiming1: vsw = 0 y10 y1 v9 t4 lh7a404-97 display-dependent turn-off delay
lh7a404 32-bit system-on-chip 60 product data sheet nxp semiconductors figure 44. tft horizontal timing 1 tft horizontal line clcdc clock (internal) lcdtiming2: csel lcdtiming2: bcd lcdlp (horiz. sync pulse) lcdtiming2:ihs lcddclk (panel data clock) lcdtiming2:pcd lcdtiming2:bcd lcdtiming2:ipc lcdtiming2:cpl lcdvd (lcd data) gpio pinmux:pdocon gpio pinmux:peocon gpio peddr note: circled numbers are lh7a404 pin numbers. lcdtiming0:hsw lcdtiming0:hbp lcdtiming0:ppl d001 d002 d.... one 'line' of lcd data dnnn lcdtiming0:hfp horizontal back porch horizontal front porch enumerated in 'lcddclks' enumerated in 'lcddclks' lh7a404-96 v2 y10
32-bit system-on-chip lh7a404 product data sheet 61 nxp semiconductors figure 45. tft vertical timing vdd see note 2 display-dependent turn-on delay 1 tft frame panel positive high-voltage supply active panel negative high-voltage supply active panel logic active panel data clock active data enable back porch enumerated in horizontal 'lines' see 'tft horizontal timing diagram' enumerated in horizontal 'lines' front porch all 'lines' for one frame vss lcdvdden (display enable for high-voltage supplies) lcddclk (panel data clock) lcdtiming2:pcd lcdtiming2: bcd lcdtiming2: ipc lcdenab (data enable) lcdtiming2:acb lcdtiming2: ioe lcdfp (vertical sync pulse) lcdtiming1: ivs pixel data and horizontal control signals for one frame notes: 1. signal polarties may vary for some displays. 2. the use of hr-clp for high-voltage power control is optional on some tft panels. 3. circled numbers are lh7a404 pin numbers. display dependent turn-off delay lcdtiming1: vbp lcdtiming1: lpp lcdtiming1: vfp lcdtiming1: vsw y10 y1 v9 t4 lh7a404-95
lh7a404 32-bit system-on-chip 62 product data sheet nxp semiconductors figure 46. ad-tft and hr-tft horizontal timing figure 47. ad-tft and hr-tft timing 1 ad-tft or hr-tft horizontal line timing0:hsw timing0:hsw + timing0:hbp pixel data 1 lcddclk 002 003 004 005 006 318317 319 320 001 1 lcddclk alitiming1:lpdel alitiming1:pscls alitiming1:revdel alitiming2:ps2cls2 alitiming2:spldel 002 003 004 005 006 007 008 320 001 clcdc clock (internal) periphclksel2:lcsrc periphclkctrl2:lcdclk lcdclkprescale:lcdpsval (shown for reference) lcdlp (horizontal sync pulse) inputs to the ali from the clcdc outputs from the ali to the panel lcddclk (panel data clock) timing2:pcd timing2:bcd timing2:ipc timing2:cpl lcdvd[17:0] 16 (timing0:ppl+1) lcddclk (delayed for hr-tft) lcdvd[17:0] (delayed for hr-tft) lcdspl (line start pulse left) lcdlp (horizontal sync pulse) lcdcls lcdps lcdrev lcdenab (internal data enable) y10 v3 u3 v5 w3 v2 note: circled numbers are lh7a404 pin numbers. lh7a404-188 lcdsps (vertical sync) lcdhrlp (horizontal sync) lcdvd (lcd data) lcdspl lh7a404-78 lcdtiming1:vsw 1.5 s - 4 s 2x h-line t4 v2 v3
32-bit system-on-chip lh7a404 product data sheet 63 nxp semiconductors clock and state controller (csc) waveforms figure 48 shows the behavior of the lh7a404 when coming out of reset or power-on. table 13 gives the timing parameters. at power-on, npor must be held low until the 32.768 khz oscillator is stab le, and must be deasserted at least two 1 hz clock periods before the wakeup signal is asserted. once the 14.7456 mh z oscillator is stable, the plls require 250 s to lock. on transition from standby to run (including a cold boot), the wakeup pin must not be asserted for two 1 hz clock periods after assertion of npor to allow time for sampling batok and nextpwr. the delay prevents a false ?battery good? indication caused by alkaline battery recovery that can immediately follow a battery-low switch off. nresetout timing sequence timing for the nresetout sequence is shown for each of the three reset triggers (npor, nureset, and npwrfl) in figure 49 through figure 51, and timing values are presented in table 14 through table 16. note: *vddc = vddcmin note: * the timing relationship is specified as a cycle-based timing. due to variati ons in crystal input clock jitter, power rail noise and i/o conditioning these timings will vary marginal ly. it is recommended that designers table 13. reset ac timing parameter description min. max. unit tosc32 (32 khz) 32.768 khz oscillator stabilization time after power on* 550 ms tosc14 (14 mhz) 14.7456 mhz oscillator stabilization time after wakeup 2.5 ms figure 48. pll start-up lh7a404-22 tosc32 vddc vddcmin xtal32 npor tosc14 xtal14 wakeup
lh7a404 32-bit system-on-chip 64 product data sheet nxp semiconductors add some timing margin to avoid any possible corner case condition. note: * the timing relationship is specified as a cycle-based timing. due to variati ons in crystal input clock jitter, power rail noise and i/o conditioning these timings will vary marginal ly. it is recommended that designers figure 49. nresetout timing for npor trigger table 14. nresetout timing values for npor trigger signal min. typ. max. units description tda_npor_nrsto 30 ns npor to nresetout assertion delay tdd_npor_nrsto 30 ns npor to nresetout deassertion delay tdd_npor_wkup 2 1 hz periods* npor deassertion to wakeup assert delay ta_wkup 4 xtal32 periods* wakeup assertion time tda_npor_clken 30 ns nureset assertion to clken deassertion delay tda_wkup_clken 2 4 xtal32 periods* wakeup to clken assertion delay npor wakeup nresetout clken tdd_npor_wkup ta_wkup tda_npor_clken tda_npor_nrsto tda_wkup_clken lh7a404-202 tdd_npor_nrsto trigger point
32-bit system-on-chip lh7a404 product data sheet 65 nxp semiconductors add some timing margin to avoid any possible corner case condition. note: * the timing relationship is specified as a cycle-based timing. due to variati ons in crystal input clock jitter, power rail noise and i/o conditioning these timings will vary marginal ly. it is recommended that designers figure 50. nresetout timing for nureset trigger table 15. nresetout timing values for nureset trigger signal min. typ. max. units description tda_nureset_nrsto 2 4 xtal32 periods* n ureset to nresetout assertion delay tdd_nureset_nrsto 0 2 xtal32 periods* nureset to nreset out deassertion delay ta_nureset 4 xtal32 periods* nureset assertion time tdd_nureset_wkup 2 xtal32 pe riods* nureset deassertion to wakeup assertion delay ta_wkup 4 xtal32 periods* wakeup assertion time tda_nureset_clken 2 4 xtal32 periods* nureset assertion to clken deassertion delay tda_wkup_clken 2 4 xtal32 periods* wakeup to clken assertion delay nureset wakeup nresetout clken tdd_nureset_wkup ta_wkup ta_nureset tda_nureset_clken tda_nureset_nrsto tda_wkup_clken lh7a404-201 tdd_nureset_nrsto trigger point
lh7a404 32-bit system-on-chip 66 product data sheet nxp semiconductors add some timing margin to avoid any possible corner case condition. figure 51. nresetout timi ng for npwrfl trigger table 16. nresetout timing values for npwrfl trigger signal min. typ. max. units* description tda_npwrfl_nrsto 2 4 xtal3 2 periods npwrfl to nresetout assertion delay ta_nrsto 2 xtal32 periods nresetout assertion time ta_npwrfl 4 xtal32 periods npwrfl assertion time tdd_npwrfl_wkup 2 1 hz pe riods npwrfl deassertion to wakeup assertion delay ta_wkup 4 xtal32 periods wakeup assertion time tda_npwrfl_clken 2 4 xtal32 periods npwrfl assertion to clken deassertion delay tda_wkup_clken 2 4 xtal32 periods wakeup to clken assertion delay ta_npwrfl npwrfl trigger point wakeup nresetout clken tdd_npwrfl_wkup ta_wkup tda_wkup_clken ta_nrsto lh7a404-200 tda_npwrfl_clken tda_npwrfl_nrsto
32-bit system-on-chip lh7a404 product data sheet 67 nxp semiconductors reference oscillator circuit design figure 52 and figure 53 show a reference oscillator design for both the 32.768 khz and 14.7456 mhz clocks. low operating temperatures and noise immunity the junction temperature, tj, is the operating tem- perature of the transistors in the integrated circuit. the switching speed of the cmos circuitry within the soc depends partly on tj, and the lower the operating tem- perature, the faster the cmos circuits will switch. increased switching noise generated by faster switch- ing circuits could affect the overall system stability. the amount of switching noise is directly affected by the application executed on the soc. nxp suggests that users implementing a system to meet the full ? 40 c to +85c specification use an exter- nal oscillator rather than a crystal to drive the system clock input of the system-on-chip. this change from crystal to oscillator will increase the robustness (ie, noise immunity of the clock input to the soc). figure 52. 32.768 khz external oscillator components and schematic enable xtalin xtalout gnd notes: 1. y1 is a parallel-resonant type crystal. (see table) 2. the nominal values for c1 and c2 shown are for a crystal specified at 12.5 pf load capacitance (cl). 3. the values for c1 and c2 are dependent upon the cystal's specified load capacitance and pcb stray capacitance. 4. r1 must be in the circuit. 5. ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. tolerance for r1, c1, c2 is 5%. gnd 32.768 khz 18 m lh7a404-168 parameter description 32.768 khz crystal tolerance aging load capacitance esr (max.) drive level reference crystal parallel mode 30 ppm 3 ppm 12.5 pf 50 k 1.0 w (max.) mtron sx1555 or equivalent c1 15 pf c2 18 pf r1 y1 internal to the lh7a404 external to the lh7a404 reference crystal specifications
lh7a404 32-bit system-on-chip 68 product data sheet nxp semiconductors figure 53. 14.7456 mhz external oscillator components and schematic enable xtalin xtalout gnd notes: 1. y1 is a parallel-resonant type crystal. (see table) 2. the nominal values for c1 and c2 shown are for a crystal specified at 18 pf load capacitance (cl). 3. the values for c1 and c2 are dependent upon the cystal's specified load capacitance and pcb stray capacitance. 4. r1 must be in the circuit. 5. ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. tolerance for r1, c1, c2 is 5%. gnd 14.7456 mhz 1 m lh7a404-167 c1 18 pf c2 22 pf r1 y1 internal to the lh7a404 external to the lh7a404 parameter description 14.7456 mhz crystal tolerance stability aging load capacitance esr (max.) drive level reference crystal (at-cut) parallel mode 50 ppm 100 ppm 5 ppm 18 pf 40 100 w (max.) mtron sx2050 or equivalent reference crystal specifications
32-bit system-on-chip lh7a404 product data sheet 69 nxp semiconductors printed circuit b oard layout practices lh7a404 power supply decoupling the lh7a404 has separate power and ground pins for different internal circuitry sections. the vdd and vss pins supply power to i/o buffers, while vddc and vssc supply power to the co re logic, and vdda/vssa supply analog power to the plls. each of the vdd and vddc pins must be provided with a low impedance path to the corresponding board power supply. likewise, the vss and vssc pins must be provided with a low impedance path to the board ground. each power supply must be decoupled to ground using at least one 0.1 ? f high frequency capacitor located as close as possibl e to a vddx-vssx pin pair on each of the four sides of the chip. if room on the cir- cuit board allows, add one 0.01 ? f high frequency capacitor near each vddx-vssx pair on the chip. to be effective, the capacitor leads and associated circuit board traces connecting to the chip vddx-vssx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. there must be one bulk 10 ? f capacitor for each power supply placed near one side of the chip. reference pll, vdda, vssa filter the vdda pins supply power to the chip pll cir- cuitry. vssa is the ground return path for the pll cir- cuit. nxp recommends a low-pass filter attached as shown in figure 54. the values of the inductor and capacitors are not critical. the low-pass filter prevents high frequency noise from adversely affecting the pll circuits. the distance from the ic pin to the high fre- quency capacitor should be as short as possible. unused input signal conditioning floating input signals can cause excessive power consumption. unused inputs without internal pull-up or pull-down resistors should be pulled up or down exter- nally, to tie the signal to its inactive state. nxp recom- mends using no larger than 33 k ? . some gpio signals may default to inputs. if the pins that carry these signals are unused, software can pro- gram these signals as outputs, eliminating the need for pull-ups or pull-downs. power consumption may be higher than expected until software completes pro- gramming the gpio. some lh7a404 inputs have inter- nal pull-ups or pull-downs. if unused, these inputs do not require external conditioning. other circuit board layout practices all outputs have fast rise and fall times. printed cir- cuit trace interconnection length must therefore be reduced to minimize overshoo t, undershoot and reflec- tions caused by transmission line effects of these fast output switching times. this recommendation particu- larly applies to the address and data buses. when considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. capacit ance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. attention to power supply decoupling and printed cir- cuit board layout becomes mo re critical in systems with higher capacitive loads. as these capacitive loads increase, transient currents in the power supply and ground return paths also increase. figure 54. vdda, vssa filter circuit lh7a404-169 vddax vddc vssax 22 f vddc (source) 0.1 f + lh7a404 10 h
lh7a404 32-bit system-on-chip 70 product data sheet nxp semiconductors package specifications figure 55. package outline sot1021-1 (lfbga324) references outline version european projection issue date iec jedec jeita sot1021-1 sot1021-1 07-07-07 07-07-07 unit a max mm 1.7 0.4 0.3 1.35 1.15 17.1 16.9 17.1 16.9 0.8 15.2 0.15 0.08 0.1 a 1 dimensions (mm are the original dimensions) lfbga324: plastic low profile fine-pitch ball grid array package; 324 balls 0 5 10 mm scale a 2 b 0.5 0.4 d e e e 1 e 2 15.2 v w y 0.12 y 1 c y c y 1 x a b c d e f h k g l j m n p r t u v w y 246810121416 13579111315 18 20 17 19 b e 2 e 1 e e 1/2 e 1/2 e ac b ? v m c ? w m ball a1 index area detail x a a 2 a 1 b a ball a1 index area e d
important notice dear customer, as from june 1 st , 2007 nxp semiconductors has acquired the lh7xxx arm microcontrollers from sharp microelectronics. the following changes are applicable to the attached data sheet. in data sheets where the previous sharp or sharp corp oration references remain, please use the new links as shown below. for www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use salesaddresses@nxp.com (email) the copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - copyright ? ( year ) by sharp corporation. is replaced with: - ? nxp b.v. ( year ). all rights reserved. if you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com ). thank you for your cooperation and understanding, in addition to that the annex a (attached hereto) is added to the document. nxp semiconductors
32-bit system-on-chip lh7a404 product data sheet 71 nxp semiconductors revision history table 17. revision history document id release date data sheet status change notice supersedes lh7a404_n_2 20080307 product data sheet - lh7a404_n_1 modifications: ? changed status from ?preliminary? to ?product? ? fig. 19; replaced with correct figure. ? fig. 20; added timing symbols. lh7a404_n_1 20070716 preliminary data sheet - lh7a404 v1-5 12-1-2006 modifications: ? first nxp version based on the lh7a404 data sheet of 20061201
lh7a404 32-bit system-on-chip 72 product data sheet nxp semiconductors 1. legal information 1.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 1.2 definitions draft ? the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp se miconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specificatio n of the product as agreed between nxp semiconductors and its customer, unless nxp semiconductors and customer have explicitly agreed other wise in writing. in no event however, shall an agreement be valid in whic h the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 1.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nx p semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rewo rk charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that cu stomer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconducto rs products, and nxp semiconductors accepts no liability for any assistance wit h applications or customer product design. it is customer?s sole respon sibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as for the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applications and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or an y other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this doc ument is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gene ral terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconductors products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products th at is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regul ations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semico nductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objectiv e specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the pro duct specification.
lh7a404 32-bit system-on-chip nxp semiconductors ? nxp b.v. 2008. all rights reserved. in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applications, use and specific ations, and (b) whenever customer uses the product fo r automotive applications beyond nxp semiconductors? specifications such us e shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims result ing from customer design and use of the product for automotive applicat ions beyond nxp semiconductors? standard warranty and nxp semiconductors? product specifications. 1.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 2. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com

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